Loading patent…
AssigneeAlcatel
InventorMICHEL HENRION
Estimating the term…
The invention relates to a system for asynchronously switching cells, each cell comprising a header field and a data field. At least some of the input modules comprise composite cell forming means, serving in particular to enable channel data blocks to be constructed each comprising a channel to be transmitted indication extracted from the channel data received and at least one synchronous channel identifier associated with said channel to be transmitted indication, and means for selectively multiplexing channel data blocks intended for a common destination, in the data field of at least one composite cell. At least some of said output modules comprise means for processing said composite cells, comprising means for extracting and recognizing said received channel data blocks by means of said associated synchronous channel identifiers, and means for transmitting to at least one outgoing link the channel data belonging to the various channels.
A system for asynchronously switching cells each comprising a header field and a data field, of the type interconnecting incoming links and outgoing links, each of said links multiplexing data belonging to at least two synchronous channels, said system comprising input port modules and output port modules interconnected by at least one stage of intermediate switching elements, wherein:
An input port module for use in a system for asynchronously switching cells each comprising a header field and a data field, of the type interconnecting incoming links and outgoing links, each of said links multiplexing data belonging to at least two synchronous channels, said system comprising input port modules and output port modules interconnected by at least one stage of intermediate switching elements,
An output port module for a system for asynchronously switching cells each comprising a header field and a data field, which system is of the type interconnecting incoming links and outgoing links, each of said links multiplexing data belonging to at least two synchronous channels, said system comprising input port modules and output port modules interconnected by at least one stage of intermediate switching elements, each output module comprising means for processing said composite cells, comprising:
A method of asynchronously switching cells each comprising a header field and a data field, using a system interconnecting incoming links and outgoing links, each of said links multiplexing data belonging to at least two synchronous channels, said system comprising input port modules and output port modules interconnected by at least one stage of switching elements,
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
Backward citations are indexed for grants only.
Drawings are temporarily unavailable. Open the PDF at USPTO
Peripheral units, e.g. input or output ports: header conversion, routing tables or routing tags
Packet switching elements: peripheral units, e.g. input or output ports
Peripheral units, e.g. input or output ports: aTM peripheral units, e.g. policing, insertion or extraction
Packet switching elements: routing or path finding in a switch fabric
Term end not estimated
USPTO file history isn’t available for this patent, so only indexed dates are shown.
The field of the invention is that of transferring and asynchronously switching cells. In particular, the invention is typically concerned with transferring synchronous channels (for example, 64 kbit/s channels of a digital multiplex) using asynchronous cell switches originally designed for switching broadband services.
In a situation of this kind, an essential condition to be complied with is the transfer delay across a switching node for each synchronous channel (ITU Recommendation Q-551 specifies an average transfer delay of 900 μs, for example, with 95% of 1500 μs or less). This is the case in particular when using standardized ATM cells, which would imply a cell assembly time of 6 μs for clustering 48 samples (each on 8 bits) of a 64 kbit/s channel.
Various approaches to reducing cell assembly time have already been proposed, whereby each cell to be switched contains no more than one sample of the same channel.
Other features and advantages of the invention will become more clearly apparent after reading the following description of a preferred embodiment of the invention which is given by way of illustrative and non-limited example only and with reference to the accompanying drawings, in which:
FIG. 1 is a simplified diagram of a switching system to which the invention can be applied,
FIG. 2 is a functional block diagram of an input CCTM of the invention,
The following abbreviations are used in the remainder of this description:
ASC: asynchronous switching center,
CCTM: terminal (input or output) port module,