Random access memory architecture and serial interface with continuous packet handling capability

#As the need for bandwidth expands in information and communication networks, bottlenecks develop in the switching hardware due to increases in the number of ports and throughput per port in routing. To handle the increased bandwidth, architectures arose that rely upon increased internal bus widths, increased bandwidths on the busses, and decentralized processing. A block diagram of an example of the architecture of a known router system 100 is shown in FIG. 1. Incoming packets can be temporarily stored in a local buffer 102 until one or more network layer processors, shown as application specific integrated circuits (ASICs) 104 and 106, classifies and determines the forwarding address of the packet. The packets are then routed to the target destination.

#Buffer 102 includes gigabytes of SRAM arranged in a very wide data bus (512 bits or more) 108 to allow several simultaneous search operations. Router system 100 analyzes the headers of incoming packets for the appropriate types of operations to be performed on the packet. In the case of TCP/IP route look-up, for example, router system 100 matches a combination of source/destination addresses with entries in a routing table for an exact match or a longest prefix match. Content addressable memory (CAM) 110 offloads ASIC 104 by processing a limited set of lookup instructions. In other applications such as load balancing and URL routing, router system 100 performs more complex search rules and routing data structures.

#A successful search will result in router system 100 modifying the header and optionally, the payload, with new information. A packet header may be modified for its output port/queue, output connection, or additional labels for switching, for example. The packets are then queued by priority as well as latency to absorb the time needed to implement the search/modify steps. Output queuing reorders packets in the event multiple packets are searched in parallel.

#FIG. 1 is a block diagram of an example of components included in a high speed router known in the art.

#FIG. 2 is a block diagram of components included in a router according to an embodiment of the present invention.

#FIG. 3a is a block diagram of an example of a SRAM device that can be utilized in the router of FIG. 2.

#A configuration of static random access memory (SRAM) devices in accordance with an embodiment of the present invention replaces the data bus 108 (FIG. 1) with high speed, point-to-point, serial data connections. Accordingly, the pin count on the controlling ASIC 104 (FIG. 1) can be significantly reduced while simultaneously achieving at least an order of magnitude increase in total bandwidth. Further, increasing the memory capacity of SRAM 102 (FIG. 1) adds bus loading on bus 108 and possibly extra pins on ASIC 104. Further, increasing the size and number of memory storage devices in SRAM 102 creates difficulties in routing bus 108 and address distribution. SRAM devices configured in accordance with an embodiment of the present invention allow an increase in the amount of memory without requiring additional pins on an ASIC and can be distributed serially in chains that are connected to the ASIC at both ends. Such a configuration simplifies real estate problems in the vicinity of the ASIC and alleviates problems associated with routing additional bus lines to ASIC 104. Further, the bandwidth per pin of an ASIC configured in accordance with embodiments of the present invention can be significantly increased, and memory reads and writes can occur simultaneously and continuously as further described hereinbelow.

#Referring now to FIG. 2, a block diagram of components included in a router 200 according to an embodiment of the present invention is shown. Router 200 includes an ASIC 202, a CAM 110, SRAM devices 204 associated with CAM 110, a bank of SRAM devices 206, and a switch 208. Each physical input has a direct connection to ASIC 202. ASIC 202 transmits the header from each packet to CAM 110 for translation, and stores the rest of the packet, also referred to as the payload, in the bank of SRAM devices 206. The payload remains in the bank of SRAM devices 206 until CAM 110 returns the header with the new routing information for the packet to ASIC 202. ASIC 202 retrieves the payload, combines the new header with the corresponding payload, and transmits the packet to switch 208 via the bank of SRAM devices 206.

#FIG. 3a is a block diagram of an embodiment of an SRAM device 300 that can be utilized in the bank of SRAM devices 206 of FIG. 2. In the embodiment shown, data is transmitted directly from a write input port 302 to a write output port 304 under all conditions. Control data, write data, and read requests are input to SRAM device 300 through write input port 302. When a valid write command is in progress, the packet is transmitted to a decoder and phase lock loop (PLL) 306. The data and the address where the data will be stored in an SRAM module 308 is decoded from the packet and transmitted to SRAM module 308, which stores the data.