Method for cell search under effect of high clock offset
AssigneeAccton Technology Corporation
InventorsJan-Shin Ho, Wern-Ho Sheen
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AssigneeAccton Technology Corporation
InventorsJan-Shin Ho, Wern-Ho Sheen
Estimating the term…
The present invention discloses a cell search method for a CDMA system, using a three-stage cell search. The method comprises matching an incoming signal from the base station, wherein the frequency of the incoming signal having an uncertain range; over-sampling the incoming signal N times against a chip rate and outputting the N over-samples; down-sampling the incoming signal and outputting N over-samples to a first stage, a second stage and a third stage. The first stage further comprises selecting a first group of slot boundaries as a first group of candidates after pre-selection, and the first group of candidates transmitting to a deciding selection stage of the first stage and the second stage to be continuously processed. The cell search method of the present invention can be used to reduce the effect of clock offset on the performance of cell search and to accomplish fast cell search.
A cell search method for use in a wideband code division multiple access (W-CDMA) system, the cell search method comprising:
A multi-dwell pipeline cell search method for use in a wideband code division multiple access (W-CDMA) system, the multiple-dwell pipeline cell search method comprising:
Dependencies are inferred from the claim text.
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1. Field of the Present Invention
The present invention relates to a cell search method suitable for a code division multiple access (CDMA) system. More particularly, the present invention provides a cell search method suitable for a wideband CDMA (W-CDMA) system that can reduce the clock offset effects in the system.
2. Description of the Related Art
FIG. 1 a schematic view illustrating the frame structure of a 3GPP wide-band CDMA system;
FIG. 2 is a schematic diagram illustrating a serial search method used in a 3GPP W-CDMA system in the prior art, in which the processing time of each stage being 10 ms;
FIG. 3 is a simplified schematic diagram illustrating a pipelined cell search method in the prior art, in which the three stages of different trials are concurrently conducted (i.e. three-stage cell search are operated in parallel);
Whenever possible in the following description, like reference numerals will refer to like elements and parts unless otherwise illustrated.
Referring to FIG. 5, a diagram schematically illustrates a multiple-dwell pipeline search process in a cell search method according to the embodiment of the prevent invention. As illustrated, the scheme includes a plurality of trials, and each illustrated block represents a stage. For example, the block 511a and block 511b represent the first stage, the block 512 represents the second stage, and the block 513 represents the third stage respectively.
The communication system of the prevent present invention preferably implements, but is not limited to, a total of 512 scrambling codes that are used to in downlink within the different cells, these scrambling codes being periodically transmitted by the cell sites. In this embodiment, the scrambling codes are divided into, for example, 64 code groups, each code group having 8 codes. Furthermore, each code has a length of, for example, 38400 chips, which therefore extends to the entire frame.
Multi-step acquisition, e.g. multi-dwell, coarse-fine or validation: multi-dwell schemes, i.e. multiple accumulation times
Synchronisation aspects: code identification
Synchronisation aspects: cell search, e.g. using a three-step approach
With code phase acquisition: with increased resolution, i.e. higher than half a chip
Term end not estimated