Loading patent…
AssigneeNone recorded
InventorsS. Paul Tucker, Edmundo Rojas
Estimating the term…
An early detection system is presented in which flow control logic is used to continually assess the capacity of a buffer memory. The flow control logic maintains an update of the buffer memory based on the buffer memories ability to store information associated with one of eight virtual lanes. As a result of the assessment, the flow control logic is capable of generating an early full detect signal. The early full detect signal denotes the capability of the buffer memory to hold packet information in a specific virtual lane. Packet checker logic receives the early full detect signal and assesses the first byte (e.g. first three bits) of a packet header, to determine whether the buffer memory can store information. If the packet passes the early detect test a second test is performed to determine if the buffer memory has enough space to store the packet. Should the buffer memory be unable to store information, the packet is discarded. If there is enough space in the buffer memory to store information, additional processing is performed to determine if the buffer memory has enough space to store the packet. As a result of the foregoing method and apparatus, several processing cycles are saved in processing the packet.
A system comprising:
A method of operating a system comprising the steps of:
A system comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
No related US applications are recorded in the indexed filing history.
Backward citations are indexed for grants only.
Flow control; Congestion control: by discarding or delaying data units, e.g. packets or frames
Flow control; Congestion control: in combination with information about buffer occupancy at either end or at transit nodes
Packet switching elements: buffering arrangements
Digital communication
Term end not estimated
1. Field of the Invention
This invention relates to packet processing. Specifically, the present invention relates to data packet flow control.
2. Description of the Related Art
FIG. 1 is a diagram of an Infiniband stack overlaid on an Open System Interconnection (OSI) protocol stack.
FIG. 2 is a high-level block diagram of the present invention.
FIG. 3 is a block diagram of an embodiment of the present invention.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
The method and apparatus of the present invention is discussed within the context of an Infiniband (e.g. Infiniband Release 1.0, 2000, by Infiniband Trade Association) Architecture. Specifically, one embodiment of the present invention is implemented in a switch. However, it should be appreciated that the present invention may be implemented with respect to other standards compliant technologies and may be implemented in a variety of communications technologies such as switches, routers, channel adapters, repeaters and links that interconnect switches, routers, repeaters and channel adapters.
FIG. 1 presents an Infiniband protocol stack within the context of the Open System Interconnection (OSI) model, which has been promulgated by the International Standards Organization (ISO). End-Nodes 100 and 106 are displayed. The end-nodes, 100 and 106 communicate across a switch 102 and a router 104. The OSI model defines a physical layer 108, a link layer 110, a network layer 112, a transport layer 114, and upper level protocol layers 116. The Infiniband specification defines a media access control layer 118, a link-encoding layer 120, a network layer 122 and an Infiniband Architecture (IBA) Operations Layer 124.