US 2003/0193832 A1 · Semiconductor memory apparatus simultaneously accessible via multi-ports

Abstract

A dual-port semiconductor memory apparatus constructed by a core circuit and a plurality of ports, different row blocks of which in the same column block of the core circuit are simultaneously accessible. Since each of the ports is provided with a global data bus, different row blocks of the same column block can be accessed via both ports by selectively activating a column line corresponding to a port and another column line corresponding to another port.

Drawings

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Drawings

Claims7

Dependent claims

A semiconductor memory apparatus, comprising:

a first I/O port and a second I/O port;
a cell array circuit divided into a plurality of column blocks and a plurality of row blocks;
a first column line and a second column line corresponding to said first I/O port and said second I/O port, respectively;
a first global data bus and a second global data bus corresponding to said first I/O port and said second I/O port, respectively, said first global data bus and said second global data bus being provided to each one of the plurality of column blocks;
a first bus connection gate circuit that connects a sense amp of one of the plurality of row blocks selected in response to an access through said first I/O port, said sense amp being selected by said first column line, to said first global data bus;
and
a second bus connection gate circuit that connects a sense amp of one of the plurality of row blocks selected in response to an access through said second I/O port, said sense amp being selected by said second column line, to said second global data bus.

4 more elements

A semiconductor memory apparatus, comprising:

a first I/O port and a second I/O port;
a sense amp amplifying a data voltage on a bit line;
a first column line and a second column line corresponding to said first I/O port and said second I/O port, respectively;
a first column gate and a second column gate correspondingly provided to said first column line and said second column line, respectively, said first column gate and said second column gate becoming conductive in response to an activation of the corresponding column line;
a first local data bus and a second local data bus corresponding to said first I/O port and said second I/O port, respectively, said first local data bus and said second local data bus being connected to said sense amp via said first column gate and said second column gate, respectively;
a first global data bus and a second global data bus corresponding to said first I/O port and said second I/O port, respectively;
a first bus connection gate circuit connecting said first local data bus to said first global data bus;
and
a second bus connection gate circuit connecting said second local data bus to said second global data bus.

6 more elements

Dependencies are inferred from the claim text.

Description3,748 words

Summary931 words

#1. Field of the Invention

#The present invention generally relates to a semiconductor memory apparatus, and particularly, to a dual-port type semiconductor memory apparatus.

#2. Description of the Related Art

Brief description of the drawings6 figures

#FIG. 1 is a block diagram showing the construction of a dual-port type semiconductor memory apparatus according to an embodiment of the present invention;

#FIG. 2 is a schematic diagram showing the construction of a memory cell array according to an embodiment of the present invention;

#FIG. 3 is a schematic diagram showing the construction of a memory block according to an embodiment of the present invention;

Detailed description2,668 words

#A detailed description of an embodiment of the present invention will be given below.

#FIG. 1 is a block diagram showing the construction of a dual-port memory according to an embodiment of the present invention.

#The dual-port memory 10 of FIG. 1 includes an address decoder 11 for the left port, an address decoder 12 for the right port, an input and output (I/O) controller circuit 13 for the left port, an I/O port 14 for the right port, a timing control arbiter 15, and a cell array circuit 16. The dual-port memory 10 is provided with address pins ADDL, data I/O pins DQL, control signal pins CNTLL, and a busy output pin BUSYL for the left port, and address pins ADDR, data I/O pins DQR, control signal pins CNTLR, and a busy output pin BUSYR for the right port. Commands such as a read command READ, a write command WRITE, a stand-by command STANDBY are transferred as control signals. The cell array circuit 16 of the dual-port memory 10 is accessible through the left port and the right port independently.

Facts

Application

10/345,373Filed 16 Jan 2003

Priority

JP 2002-11027512 Apr 2002

Published

16 Oct 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification3 codes

G11C 8/16
Arrangements for selecting an address in a digital store: multiple access memory array, e.g. addressing one storage element via at least two…
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C
Static stores

Timeline

12 Apr 2002Priority claimedJP 2002-110275
16 Jan 2003Application filedUS 10/345,373
16 Jan 2003Assigned to Fujitsu Limitedassignment of assignor's interest
16 Oct 2003Published
12 Dec 2008Assigned to Fujitsu Microelectronics Limitedassignment of assignor's interest
22 Jul 2010Assigned to Fujitsu Semiconductor Limitedchange of name
27 Apr 2015Assigned to Socionext Inc.assignment of assignor's interest

Semiconductor memory apparatus simultaneously accessible via multi-ports

Life of this patent

Semiconductor memory apparatus simultaneously accessible via multi-ports

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims7

Description3,748 words

Drawings

Classification3 codes

Life of this patent

Description3,748 words