Method and system for writing data in an MRAM memory device

#The present invention relates generally to integrated circuits, and more specifically to the storage of data in integrated circuits.

#Computer systems, video games, electronic appliances, digital cameras, and myriad other electronic devices include memory for storing data related to the use and operation of the device. A variety of different memory types are utilized in these devices, such as read only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory (FLASH), and mass storage such as hard disks and CD-ROM or CD-RW drives. Each memory type has characteristics that better suit that type to particular applications. For example, DRAM is slower than SRAM but is nonetheless utilized as system memory in most computer systems because DRAM is inexpensive and provides high density storage, thus allowing large amounts of data to be stored relatively cheaply. A memory characteristic that often times determines whether a given type of memory is suitable for a given application is the volatile nature of the storage. Both DRAM and SRAM are volatile forms of data storage, which means the memories require power to retain the stored data. In contrast, mass storage devices such as hard disks and CD drives are nonvolatile storage devices, meaning the devices retain data even when power is removed.

#Current mass storage devices are relatively inexpensive and high density, providing reliable long term data storage at relatively cheap. Such mass storage devices are, however, physically large and contain numerous moving parts, which reduces the reliability of the devices. Moreover, existing mass storage devices are relatively slow, which slows the operation of the computer system or other electronic device containing the mass storage device. As a result, other technologies are being developed to provide long term nonvolatile data storage, and, ideally, such technologies would also be fast and cheap enough for use in system memory as well. The use of FLASH, which provides nonvolatile storage, is increasing popular in many electronic devices such as digital cameras. While FLASH provides nonvolatile storage, FLASH is too slow for use as system memory and the use of FLASH for mass storage is impractical, due in part to the duration for which the FLASH can reliably store data as well as limits on the number of times data can be written to and read from FLASH.

#FIG. 1A is a functional block diagram showing a portion of a conventional MRAM array.

#FIG. 1B is a partial cross-sectional isometric view of the portion of the MRAM array of FIG. 1A.

#FIG. 1C is a cross-sectional view illustrating in more detail the magnetic fields applied to the selected memory cell in array of FIG. 1B during programming of the selected memory cell.

#FIG. 2 is a block diagram illustrating a portion of an MRAM array 200 including a switching network 202 that routes a column current ICOL applied to a selected bit line BL through adjacent bit lines in an opposite direction to reduce the likelihood of undesirably programming memory cells 204 adjacent a selected memory cell, as will be explained in more detail below. In the following description, certain details are set forth to provide a sufficient understanding of the present invention. However, it will be clear to one skilled in the art that the present invention may be practiced without these particular details. In other instances, well-known circuits and their operation have not been shown or described in detail to avoid unnecessarily obscuring the present invention.

#The MRAM array 200 includes a plurality of word lines WL1-M and a plurality of bit lines BL1-N, with each memory cell 204 in a respective row being coupled to a corresponding word line and each memory cell in a respective column being coupled to a corresponding bit line. Only word lines WL1-3 and bit lines BL1-4 are illustrated in FIG. 2. The word lines WL are positioned parallel to an X-axis and the bit lines BL positioned parallel to an orthogonal Y-axis, in the same way as previously described with reference to the conventional array 100 of FIGS. 1A-D. The switching network 202 includes a plurality of switches S1-SN−1, each switch being coupled between a pair of adjacent bit lines BL at one end of the bit lines. The switching network 202 includes N−1 switches, where N equals the number of bit lines BL in the array 200, although only the switches S1-S4 are shown in FIG. 2. Each of the switches S1-S4 receives a switch control signal SC which, when activated, turns ON each switch to thereby couple adjacent bit lines BL together. When the switch control signal SC is inactive, each switch S1-SN−1 is turned OFF, isolating adjacent bit lines BL from one another.

#In operation of the MRAM array 200 during write operations, a row current IROW is applied to a selected word line WL and a column current ICOL is applied to a selected bit line BL. FIG. 2 illustrates a situation where the word line WL2 and the bit line BL2 are selected, with the row current applied to the word line WL2 being designated IROW2 and the column current applied to bit line BL2 being designated ICOL2. The selected word line WL2 is coupled to ground at the end opposite the end to which the row current IROW2 is applied, and all unselected word lines WL, which are all word lines except word line WL2, are coupled also coupled to ground. The unselected bit lines BL, which are all bit lines except the bit line BL2, are also coupled to ground. During write operations, the switch control signal SC is activated, turning ON the switches S1-SN−1 and thereby coupling the bit lines BL together at the ends opposite the end at which the column current ICOL2 is applied and opposite the ends at which the unselected bit lines BL are coupled to ground.