Wordline driven method for sensing data in a resistive memory array

A memory device comprising:

• a plurality of first conductors;
• a plurality of second conductors;
• a plurality of memory cells, each connected between a respective one of said plurality of first and second conductors, each of said memory cells storing a logic state as a respective resistance value;
• a bias voltage source switchingly coupled to each of said first conductors for biasing each of said first conductors to a first voltage;
• a selection circuit for selecting one of said memory cells for a read operation, said selection circuit adapted to drive the one of said first conductors connected to said selected memory cell to a second voltage higher than said first voltage;
• and
• a read circuit for reading a voltage on the one of said second conductors connected to said selected memory cell to determine a logic state stored by said memory cell.

A resistive memory integrated circuit comprising:

• a plurality of row lines operatively connected to a respective plurality of switching devices, said switching devices adapted to switchingly connect said row lines alternately to ground and array voltage;
• a plurality of column lines, each of said column lines disposed in non-parallel spaced relation to said plurality of row lines to define a plurality of overlap regions;
• a plurality of amplifiers connected to said plurality of column lines respectively, said plurality of amplifiers adapted to sense a voltage on a respective column line;
• a plurality of memory cells respectively connected between said row lines and said column lines at said overlap regions;
• and
• a control circuit operatively connected to said plurality of switching devices and adapted to switch one of said devices so as to connect a respective one of said plurality of row lines to said array voltage while simultaneously maintaining the other row lines of said plurality of row lines at ground.

A method of reading data from a resistive memory device having an array of resistive memory cells, each cell coupled to an associated row line and column line comprising:

• maintaining a said array of resistive memory cells of said device at ground potential while said device is in a quiescent state;
• raising a selected row line of said array to a non-ground potential while said device is in a read state;
• and
• amplifying a voltage on a selected column line of said array while said device is in said read state to read data from a selected resistive memory cell.

A method of measuring a logic state of a resistive memory cell comprising:

• switchingly connecting a plurality of row lines of a resistive memory integrated circuit to a source of ground potential;
• at a sensing time, switching a selected one of said plurality of row lines to a source of a non-ground potential, said selected row line being connected to a selected resistive memory cell;
• and
• sensing a voltage of a selected column line of said memory integrated circuit connected to said selected resistive memory cell, said voltage corresponding to an electrical potential between said ground and non-ground potentials, said voltage representing a logic state of said selected resistive memory cell.

A method of sensing a resistance state of a resistive memory cell comprising:

• switchingly connecting a plurality of row lines to a ground potential, said plurality of row lines being connected to a respective plurality of resistive memory cells at a plurality of respective first ends of said memory cells, said plurality of resistive memory cells including a respective plurality of second ends mutually connected to a column line;
• switchingly connecting one of said plurality of row lines to an elevated potential at a switching time;
• and
• sensing a voltage on said column line during a measuring time period after said switching time, said voltage substantially determined by a resistance of one resistive memory cell connected to said row line.

A method of sensing a logic state stored in a resistive memory cell comprising:

• arranging a first resistive memory cell in a voltage divider, said voltage divider including, in addition to said first cell, a plurality of further resistive memory cells each having a first end coupled to said first cell and a second end coupled to ground;
• flowing an electrical current through said voltage divider;
• measuring an output voltage of said voltage divider;
• and
• relating said measured voltage to a logic state of said first cell.

A method of reading digital data stored as a state of a resistive memory cell comprising:

• setting the respective potentials of a plurality of row lines to ground potential, said row lines each being coupled to a respective plurality of resistive memory cells;
• setting the potential of a selected one of said plurality of row lines to a second potential above ground;
• sensing a potential of a column line coupled to one end of one memory cell of said plurality of memory cells, said one cell being coupled at another end to said row line;
• and
• determining a logic state stored by said one cell using said sensed potential.