Method and system for low power refresh of dynamic random access memories

A method of operating a DRAM device in either a high power, full density mode or a low power, half density mode, comprising:

• when operating in the full density mode, refreshing rows of memory cells in an array one-row-at-a-time at a first rate;
• when operating in the half density mode, refreshing rows of memory cells in the array two-rows-at-a-time at a second rate that is slower than the first rate;
• and
• when switching from operation in the full density mode to operation in the half density mode, transferring data from each row of the array in which data are stored to another row of memory cells.

A dynamic random access memory (“DRAM”) comprising:

• an array of memory cells arranged in rows and columns, each row of memory cells having a respective word line that is activated to couple the memory cells in the row to one of a respective pair of complimentary digit lines;
• a row decoder coupled to receive a row address and being operable to activate a word line corresponding thereto;
• a column decoder coupled to receive a column address and being operable to select a memory cell in a column corresponding thereto;
• an input/output control circuit including a sense amplifier for each column of memory cells in the array, the input/output control circuit coupling data between the memory cells in the array and a data bus;
• a row address counter coupled to the row decoder, the row address counter being operable to increment by one in a full density mode and to increment by two in a half density mode, the row address counter being operable to generate row addresses corresponding to the count of the row address counter;
• a refresh control circuit operable in either a full density mode or a half density mode, the refresh control circuit being operable to cause data to be transferred from memory cells in each row of the array in which data are stored to another row of memory cells when switching from operation in the full density mode to operation in the half density mode, the refresh control circuit further being operable to refresh each row of memory cells selected by a row address from the row address counter in the full density mode and to simultaneously refresh two rows of memory cells selected by a row address from the row address counter in the half density mode;
• and
• a refresh timer operable to control the rate at which the rows of memory cells are refreshed in the full density mode and in the half density mode.

A dynamic random access memory (“DRAM”) comprising:

• an array of memory cells arranged in rows and columns, each row of memory cells having a respective word line that is activated to couple the memory cells in the row to one of a respective pair of complimentary digit lines;
• a row decoder coupled to receive a row address and being operable to activate a word line corresponding thereto, the row decoder being operable to reorder each row address applied to the DRAM device by making the most significant bit of the row address the least significant bit of a reordered row address, and each of the remaining bits of the row address the next highest order bit of the reordered row address, the row decoder activating word lines for respective rows of memory cells according to the reordered row address;
• a column decoder coupled to receive a column address and being operable to select a memory cell in a column corresponding thereto;
• an input/output control circuit including a sense amplifier for each column of memory cells in the array, the input/output control circuit coupling data between the memory cells in the array and a data bus;
• a row address counter coupled to the row decoder, the row address counter being operable to generate row addresses corresponding to the count of the row address counter;
• a refresh control circuit operable in either a full density mode or a half density mode, the refresh control circuit being operable to cause data to be transferred from memory cells in each row of the array in which data are stored to an adjacent row of memory cells when switching from operation in the full density mode to operation in the half density mode, the refresh control circuit further being operable to refresh each row of memory cells selected by a row address from the row address counter in the full density mode and to simultaneously refresh two adjacent rows of memory cells selected by a row address from the row address counter in the half density mode;
• and
• a refresh timer operable to cause the rows of memory cells to be refreshed at a first rate in the full density mode and at a second rate in the half density mode, the second rate being slower than the first rate.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• and
• a dynamic random access memory (“DRAM”) device coupled to the processor through the processor bus, the DRAM device comprising:
• an array of memory cells arranged in rows and columns, each row of memory cells having a respective word line that is activated to couple the memory cells in the row to one of a respective pair of complimentary digit lines;
• a row decoder coupled to receive a row address and being operable to activate a word line corresponding thereto;
• a column decoder coupled to receive a column address and being operable to select a memory cell in a column corresponding thereto;
• an input/output control circuit including a sense amplifier for each column of memory cells in the array, the input/output control circuit coupling data between the memory cells in the array and a data bus;
• a row address counter coupled to the row decoder, the row address counter being operable to increment by one in a full density mode and to increment by two in a half density mode, the row address counter being operable to generate row addresses corresponding to the count of the row address counter;
• a refresh control circuit operable in either a full density mode or a half density mode, the refresh control circuit being operable to cause data to be transferred from memory cells in each row of the array in which data are stored to another row of memory cells when switching from operation in the full density mode to operation in the half density mode, the refresh control circuit further being operable to refresh each row of memory cells selected by a row address from the row address counter in the full density mode and to simultaneously refresh two rows of memory cells selected by a row address from the row address counter in the half density mode;
• and
• a refresh timer operable to control the rate at which the rows of memory cells are refreshed in the full density mode and in the half density mode.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• and
• a dynamic random access memory (“DRAM”) device coupled to the processor through the processor bus, the DRAM device comprising:
• an array of memory cells arranged in rows and columns, each row of memory cells having a respective word line that is activated to couple the memory cells in the row to one of a respective pair of complimentary digit lines;
• a row decoder coupled to receive a row address and being operable to activate a word line corresponding thereto, the row decoder being operable to reorder each row address applied to the DRAM device by making the most significant bit of the row address the least significant bit of a reordered row address, and each of the remaining bits of the row address the next highest order bit of the reordered row address, the row decoder activating word lines for respective rows of memory cells according to the reordered row address;
• a column decoder coupled to receive a column address and being operable to select a memory cell in a column corresponding thereto;
• an input/output control circuit including a sense amplifier for each column of memory cells in the array, the input/output control circuit coupling data between memory cells in the array and a data bus;
• a row address counter coupled to the row decoder, the row address counter being operable to generate row addresses corresponding to the count of the row address counter;
• a refresh control circuit operable in either a full density mode or a half density mode, the refresh control circuit being operable to cause data to be transferred from memory cells in each row of the array in which data are stored to an adjacent row of memory cells when switching from operation in the full density mode to operation in the half density mode, the refresh control circuit further being operable to refresh each row of memory cells selected by a row address from the row address counter in the full density mode and to simultaneously refresh two adjacent rows of memory cells selected by a row address from the row address counter in the half density mode;
• and
• a refresh timer operable to cause the rows of memory cells to be refreshed at a first rate in the full density mode and at a second rate in the half density mode, the second rate being slower than the first rate.