Two-bit programmable nonvolatile memory device and methods of operating and fabricating the same

A semiconductor device comprising:

• a plurality of first device isolation layers arranged on a semiconductor substrate at regular pitches in the row and column directions;
• a plurality of second device isolation layers arranged at positions re-moved from each of the first device isolation layers by one-half such pitch in the row and column directions;
• a plurality of word lines crossing alternately over the first and second device isolation layers in parallel in the row direction, the word lines disposed at regular intervals;
• a multiple insulation layer intervened between the word lines and the semiconductor substrate, the multiple insulation layer including a charge trap insulation layer;
• first source/drain regions formed respectively at regions defined by a pair of adjacent word lines as well as a pair of adjacent first device isolation layers crossing a pair of the word lines;
• and
• second source/drain regions formed respectively at regions defined by a pair of adjacent word lines as well as a pair of adjacent second device isolation layers,
• wherein the first and second source/drain regions have substantially the same surface area.

A semiconductor device comprising:

• a plurality of device isolation layers disposed at a predetermined region of a semiconductor substrate in parallel at regular intervals in the row direction;
• a plurality of word lines crossing over the device isolation layers in the row direction, the word lines disposed in parallel at regular intervals;
• a multiple insulation layer intervened between the word lines and the semiconductor substrate, the multiple insulation layer including a charge trap insulation layer;
• and
• a plurality of source/drain regions formed respectively at regions defined by a pair of adjacent word lines and by as a pair of adjacent device isolation layers that a pair of the adjacent word lines intersect, the source/drain regions arranged in the row and column directions,
• wherein the source/drain regions formed on the semiconductor substrate have substantially the same surface area.

A method of operating a memory device comprising a plurality of word lines disposed on a semiconductor substrate in parallel and each of which includes a plurality of memory cells, as well as a plurality of bit lines crossing the word lines to be disposed in parallel and connected to one selected from source/drain regions of each word line, wherein each memory cell comprises a word line, source/drain regions formed in the semiconductor substrate of both sides of the word line, and a charge trap insulation layer intervened between the word line and the semiconductor substrate, and wherein each memory cell has one of the source/drain regions in common with one memory cell having a first word line in common as well as a pair of memory cells having a second word line that is adjacent to the first word line in common, and has another source/drain region in common with another memory cell having the first word line in common as well as a pair of memory cells having a third line that is adjacent to the first word line in common, and wherein source/drain regions of each memory cell are respectively connected to different bit lines, the method comprising:

• a first bit write operation including selecting adjacent first and second bit lines and one word line, and applying a first level voltage, a ground voltage, and a write voltage to a first bit line, a second bit line, and a selected word line, thereby writing a first bit into a region adjacent to the first bit line of the charge trap insulation layer constituting the selected memory cell;
• a second bit write operation including applying a first level voltage, a ground voltage, and a write voltage to the second bit line, the first bit line, and the selected word line, thereby writing a second bit into the charge trap insulation layer adjacent to the second bit line;
• a first bit read operation including applying a ground voltage, a second level voltage lower than the first level voltage, and a read voltage lower than the write voltage to the first bit line, the second bit line, and the selected word line;
• and
• a second bit read operation including applying a ground voltage, a second level voltage, and a read voltage to the second bit line, the first bit line, and the selected word line.

A method of operating a memory device comprising a plurality of word lines disposed on a semiconductor substrate in parallel and each of which includes a plurality of memory cells, as well as a plurality of bit lines crossing the word lines to be disposed in parallel and connected to one selected from source/drain regions of each word line, wherein each memory cell comprises the word line, source/drain regions formed in the semiconductor substrate of both sides of the word line, and a charge trap insulation layer intervened between the word line and the semiconductor substrate, and wherein each memory cell has one of the source/drain regions in common with one of memory cells of an adjacent word line, and another source/drain region in common with one of memory cells of another adjacent word line, and wherein each of the bit lines is alternately connected to source/drain regions of two adjacent rows, the method comprising:

• a first bit write operation including selecting adjacent first and second bit lines and one word line, and applying a first level voltage, a ground voltage, and a write voltage to a first bit line, a second bit line, and a selected word line, thereby writing a first bit into a region adjacent to the first bit line of the charge trap insulation layer constituting the selected memory cell;
• a second bit write operation including applying a first level voltage, a ground voltage, and a write voltage to the second bit line, the first bit line, and the selected word line, thereby writing a second bit into the charge trap insulation layer adjacent to the second bit line;
• a first bit read operation including applying a ground voltage, a second level voltage lower than the first level voltage, and a read voltage lower than the write voltage to the first bit line, the second bit line, and the selected word line;
• and
• a second bit read operation including applying a ground voltage, a second level voltage, and a read voltage to the second bit line, the first bit line, and the selected word line.

A method of fabricating a memory device comprising:

• forming a plurality of device isolation layers at a predetermined region of a semiconductor substrate at regular intervals to define active regions;
• sequentially forming a multiple insulation layer and a gate conductive layer on an entire surface of the semiconductor substrate where the device isolation layers are formed;
• successively patterning the gate conductive layer and the multiple insulation layer to form a plurality of word lines crossing the device isolation layers at regular intervals and, to form a plurality of isolated regions wherein the word lines and the device isolation layers cross each other and the semiconductor substrate of the same regions is exposed;
• and
• injecting impurities into the semiconductor substrate of the isolated regions to form a plurality of source/drain regions arranged in the row and column directions.

A method of fabricating a memory device comprising:

• forming a plurality of first device isolation layers on a semiconductor substrate at regular pitches in the row and column directions as well as a plurality of second device isolation regions at positions re-moved from each of the first device isolation layers by one-half such pitch in the row and column directions;
• forming a multiple insulation layer and a gate conductive layer on an entire surface of the semiconductor substrate where the first and second device isolation layers are formed;
• patterning the gate conductive layer and the multiple insulation layer to form a plurality of word lines crossing alternately over the first and second device isolation layers and disposed in parallel at regular intervals in the row direction;
• and
• injecting impurities into the semiconductor substrate by using the word lines as an ion implantation mask, to form first source/drain regions at regions defined by a pair of the adjacent word lines as well as a pair of the first device isolation layers crossing a pair of the word lines and, to form second source/drain regions at regions defined by a pair of the adjacent word lines as well as a pair of the second device isolation layers crossing a pair of the word lines.

A method of fabricating a memory device comprising:

• forming a plurality of device isolation layers at a predetermined region of a semiconductor substrate in parallel at regular intervals in the row direction to define active regions;
• forming a multiple insulation layer and a gate conductive layer on an entire surface of the semiconductor substrate where the device isolation layers are formed;
• patterning the gate conductive layer and the multiple insulation layer to form a plurality of word lines crossing over the device isolation layers in the row direction and disposed in parallel at regular intervals;
• injecting impurities into the semiconductor substrate by using the word lines as an ion implantation mask to form source/drain regions at regions defined by a pair of the adjacent
• word lines as well as a pair of the adjacent device isolation layers that a pair of the adjacent word lines intersect;
• and
• forming a plurality of bit lines crossing over the word lines and connected to one of the source/drain regions of each row,
• wherein each bit line is formed to be alternately connected to the source/drain regions of two adjacent rows.