US 2003/0193824 A1 · Semiconductor memory device

Abstract

A memory cell is formed of a sense access transistor for data sensing, a restore access transistor for data restoration and a memory capacitor for data storage. Sense access transistor couples the memory capacitor to a sense bit line according to a signal on a sense word line. The restore access transistor couples the memory capacitor to a restore bit line provided separate from the sense bit line according to a signal on a restore word line. Electric charges in the memory capacitor are transferred to a sense amplifier through the sense bit line and sense data in a sense amplifier is transferred to original memory capacitor through a restore amplifier and the restore access transistor. Output signal lines of the sense amplifier are electrically isolated from the sense and restore bit lines. Thereby, it is possible to reduce the access time of a semiconductor memory device.

Drawings

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Drawings

Claims18

Dependent claims

A semiconductor memory device comprising:

a plurality of memory cells, arranged in rows and columns, each including a capacitor for storing information, and first and second access transistors coupled commonly to one electrode of said capacitor;
a plurality of first word lines, arranged corresponding to the respective memory cell rows, each coupled to the first access transistors of memory cells on a corresponding row for driving the first access transistors of the memory cells on the corresponding row into a conductive state when selected;
a plurality of second word lines, arranged corresponding to the memory cell rows, each coupled to the second access transistors of the memory cells on a corresponding row for driving the second access transistors of the memory cells on the corresponding row into a conductive state when selected;
a plurality of first bit lines, arranged corresponding to the memory cell columns, each coupled to the first access transistors of memory cells on a corresponding column for transferring data transmitted through a first access transistor of a selected memory cell on the corresponding column;
a plurality of second bit lines, arranged corresponding to the memory cell columns, each coupled to the second access transistors of the memory cells on a corresponding column for transferring write data to a selected memory cell on the corresponding column;
and
a plurality of sense amplifiers, arranged corresponding to the plurality of first bit lines, each for sensing and amplifying data on a corresponding first bit line when activated;
and
a plurality of restore circuits, arranged corresponding to the plurality of second bit lines and to the plurality of first sense amplifiers, each for latching at least amplified data by a corresponding first sense amplifier to drive a corresponding second bit line according to a latch signal therein when activated.

6 more elements

A semiconductor memory device comprising:

a plurality of active regions each having a prescribed width and arranged continuously extending in a column direction;
a plurality of first bit lines arranged in parallel to the active regions;
a plurality of second bit lines arranged in parallel to said active regions, the first bit lines and the second bit lines being arranged in a prescribed sequence in a row direction in a two-dimensional layout;
a plurality of first word lines arranged in a direction intersecting with said active regions;
a plurality of second word lines arranged in a direction intersecting with the active regions and in a prescribed sequence with said plurality of said first word lines;
a plurality of first connection conductors arranged in said column direction at prescribed intervals in correspondence to said active regions, for electrically coupling corresponding active regions to corresponding first bit lines;
a plurality of second connection conductors arranged in said column direction at prescribed intervals in correspondence to said active regions, and electrically coupling corresponding active regions with corresponding second bit lines;
and
a plurality of memory cell capacitors, each having a storage electrode conductors arranged corresponding to the active region between the first conductor and the second conductor in the column direction, for electrically coupling to the corresponding active regions, the storage electrode conductor forming a part of a storage node storing data of a memory cell,
in each of said active regions, a first access transistor being formed in a region of intersection with a first word line, and a second access transistor being formed in a region of intersection with a second word line, and
each of the memory cells being formed of the first and second access transistors and a capacitor having the storage electrode conductor arranged between said first and second transistors.

8 more elements

Dependencies are inferred from the claim text.

Description24,871 words

Summary2,484 words

#1. Field of the Invention

#The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device with a memory cell structure storing data in a capacitor in the form of electric charges. More particularly, the present invention relates to a configuration and a memory cell layout for achieving high speed access to a dynamic type memory cell.

#2. Description of the Background Art

Brief description of the drawings41 figures

#FIG. 1 is a diagram showing a configuration of a main part of a semiconductor memory device according to a first embodiment of the present invention;

#FIG. 2 is a signal waveform diagram representing operations of the semiconductor memory device shown in FIG. 1;

#FIG. 3 is a diagram showing cycle times of a semiconductor memory device according to the present invention and a conventional semiconductor memory device;

Detailed description21,455 words

#First Embodiment

#FIG. 1 is a diagram showing a configuration of a main part of a semiconductor memory device according to a first embodiment of the present invention. Memory cells 1 are arranged in rows and columns in the open bit line configuration. In FIG. 1, there are representatively shown two memory cells 1R and 1L. To memory cell 1R, there are provided a sense bit line SBL_R and a restore bit line RBL_R and to memory cell 1L, there are provided a sense bit line SBL_L and a restore bit line RBL_L.

#Sense bit lines SBL_R and SBL_L are coupled to sense amplifiers 2. Sense amplifier 2, in an active state, differentially amplifies potentials on sense bit lines SBL_R and SBL_L to output the output signals thereof onto sense output lines /D_R and /D_L. Sense output lines /D_R and /SD_L are electrically isolated from sense bit lines SBL_R and SBL_L. Therefore, sense bit line SBL_R and SBL_L only transmit data of a selected memory cell, and data amplified by sense amplifier 2 is not transmitted onto sense bit lines SBL_R and SBL_L.

Facts

Application

10/319,521Filed 16 Dec 2002

Priority

JP 2002-109462(P)11 Apr 2002

Published

16 Oct 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification3 codes

G11C 11/405
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with three charge-transfer gates, e.g. MOS transistors,…
G11C 11/406
Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: management or control of the refreshing or charge-regeneration cycles
G11C
Static stores

Timeline

11 Apr 2002Priority claimedJP 2002-109462(P)
16 Dec 2002Application filedUS 10/319,521
16 Dec 2002Assigned to Mitsubishi Denki Kabushiki Kaishaassignment of assignor's interest
10 Sep 2003Assigned to Renesas Technology Corp.assignment of assignor's interest
16 Oct 2003Published
7 Apr 2004Assigned to Renesas Technology Corp.assignment of assignor's interest

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims18

Description24,871 words

Drawings

Classification3 codes

Life of this patent

Description24,871 words