Semiconductor memory device provided with test memory cell unit

Abstract

A semiconductor memory device is provided which is composed of ferroelectric memories and which allows the cycling test in the assurance number of cycles to be conducted on the entire devices during a screening test. The semiconductor memory device comprises a memory cell block composed of a memory cell unit having a plurality of memory cells, each containing a ferroelectric capacitor, and a test memory cell unit having a plurality of test memory cells. The layout pattern of the test memory cells is identical to the layout pattern of the memory cells. The test memory cell unit is arranged close to that memory cell of a plurality of memory cells which is arranged in a position in which the ferroelectric capacitor is susceptible to degradation. The memory cell unit and test memory cell unit are subjected to a first cycling test consisting of N1 cycles. Then, the test memory cell unit is subjected to a second cycling test consisting of N2 cycles. The sum (N1+N2) of the number of cycles in the first and second cycling tests is an assurance number of cycles T, where the condition of N1<N2 is satisfied.

Drawings

Dependencies are inferred from the claim text.