Redundant array architecture for word replacement in cam

#1. Field of the Invention

#The present invention relates to semiconductor computer memories, and more particularly to a redundancy architecture and technique that provides a separate array for word replacement without impacting the size or performance of content-addressable memories (CAM).

#2. Background Description

#FIG. 1 illustrates an array redundancy architecture in CAM;

#FIG. 1A shows a redundancy latch logic;

#FIG. 2 shows the details of the redundant array, redundant register array, and compare block;

#The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.

#In the present method, the word line redundancy architecture allows for a parallel search of both the default memory array and redundant memory array. During a search operation, if the hit signal in the redundant array is active (i.e. a match occurred), the index from the redundant array is translated from n-m bits to n bits, where m is the width of an address word. If a hit also occurred in the default array, the comparator provides the lowest index of occurrence. During a read/write operation a n-bit address is translated to a m bit index by the redundancy register array. The redundancy register array first checks whether the n-bit address is in the redundant array and then converts that address to a m bit index and selects it for read/write. If the m index is not in the redundant array, the read/write operation is only performed in the default array.

#The present invention avoids look-up operation complications in content-addressable memories. Therefore, the solution is to pair the redundant array with a logic block or redundant register array, which functions as a sort of a CAM within CAM. The redundant register array acts as content-addressable memory using the requested address as a checking key during read and write operations. The result of this search tells whether the requested address is stored in the separate redundant array and, if so, in which redundant entry. If found, the read/write operation to the redundant array is allowed to proceed.