Balanced MR head bias technique for magneto-resistive preamplifier operating in a single supply environment
AssigneeTexas Instruments Incorporated
InventorDavy H. Choi
Life of this patent
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Abstract
An MR head bias circuit (60) in a preamplifier includes a balanced driving circuit (62,64) for connection to the MR head (12) at respective first (66) and second (68) output nodes and impedance matching elements (72,74) to match an output impedance at each output node (66,68) to each other. The impedance matching elements (72,74) may match an output impedance at each output node (66,68) to make them substantially the same.
Claims28
An MR head bias circuit in a preamplifier comprising:
- a balanced driving circuit for connection to said MR head at respective first and second output nodes;
- and
- impedance matching elements to match an output impedance at each output node to each other, wherein said output impedance at each output node is substantially the same.
An MR head preamplifier circuit having a single power supply having a voltage supply rail and a reference voltage rail at a potential below said voltage supply rail, comprising:
- a first output terminal for connection to one side of an MR head;
- a pull-up transistor connected on one side to said first output terminal;
- a resistor connected between another side of said pull-up transistor and said voltage supply rail;
- a second output terminal for connection to another side of said MR head;
- a pull-down transistor connected on one side to said reference voltage rail and on another side to said second output terminal;
- a first impedance matching transistor having impedance characteristics similar to said pull-up transistor connected between said second output terminal and said voltage supply rail;
- and
- a second impedance matching transistor having impedance characteristics similar to said pull-down transistor connected between said first output terminal and said reference voltage rail.
An MR head bias circuit in a preamplifier circuit having a single power supply with a supply voltage and a reference voltage at a potential below said supply voltage, comprising:
- a first PMOS transistor connected on one side to a first output node for connection to one side of an MR head;
- a resistor between another side of said PMOS transistor and said supply voltage;
- a second output node for connection to another side of said MR head;
- a first NMOS transistor between said reference voltage and said second output node;
- a second PMOS transistor having impedance characteristics similar to said first PMOS transistor, between said second output node and said voltage supply;
- and
- a second NMOS transistor having impedance characteristics similar to said first NMOS transistor, between said first output node and said reference voltage.
A method for biasing an MR head, comprising:
- providing pull-up and pull-down transistors for connection to respective sides of said MR head at respective first and second output nodes;
- connecting first and second impedance matching transistors having impedance characteristics similar to impedance characteristics respectively of said pull-up and pull-down transistors respectively to said second and first output nodes, whereby respective impedances at said first and second output nodes are substantially the same.
Dependencies are inferred from the claim text.