Image sensor with readout circuit

#This invention relates to solid state active pixel image sensors, and more particularly to CMOS image sensors, e.g. having active pixels each including a photodiode and three transistors.

#An image sensor of the type having active pixels each including a photodiode and three transistors commonly uses the technique known as Correlated Double Sampling (CDS) in which two sampling steps are used whereby a reset voltage and a signal voltage for each pixel are stored on capacitors in the column, and the difference between these voltages is processed by the readout chain. CDS improves fixed pattern noise in the final image, but although the subtraction process removes low frequency pixel noise it increases high frequency noise. The requirement for two readout steps limits the maximum operating frequency of the camera, and the provision of the storage capacitors increases the column area and contributes kT/C sampling noise.

#European Patent Application 0130543.6 filed Oct. 5, 2001 by the present Assignee discloses a 3-transistor pixel image sensor using a read-reset amplifier which operates in reset mode to apply a reset voltage and in read mode it operates as a comparator.

#Embodiments of the invention will now be described, by way of example only, with reference to the drawings, in which:

#FIG. 1 is a schematic circuit diagram of one example of image sensor embodying the invention;

#FIG. 2 is a schematic circuit diagram showing part of the circuit of FIG. 1 in more detail;

#FIG. 1 shows, by way of example, a 3×3 active pixel array. Each pixel 10 includes a photodiode 12 and a transistor pair MN2, MR1 which forms the upper half of a NMOS source follower structure. Each column contains a column line 16 and a second column line 20. To minimize the capacitance of these two lines, they are best routed in layers of metal with the Vx metal (line 16) above the VRT metal (line 20).

#The two column lines 16 and 20 are connected to a Read-Reset Amplifier (RRComp) circuit 22. The RRComp circuit 22 has two modes controlled by signals ReadMode and ResetMode. When a row of pixels is to be reset to a reference voltage VRT, these signals are ReadMode=0 and ResetMode=1 and the RRComp 22 functions as a unity gain buffer amplifier. When a row of pixel voltages is to be read out and converted into digital form, ReadMode=1 and ResetMode=0 and the RRComp 22 functions as an open loop amplifier or comparator. By feeding a ramp voltage to the input of each RRComp 22 the system functions as a single slope A-D converter.

#FIG. 2 shows the schematic of the RRComp circuit 22. One such circuit is contained at the base of each column and serves a column of pixels 10, one of which is seen in FIG. 2. The RRComp circuit 22 is essentially a single stage amplifier which uses transistors MR1 and MN2 in the pixel as one half of a differential pair, and the column current source MCS1 and MCS2 as the long tail pair bias current. Transistors MP1 and MP2 form a current source load which can be configured via transistors MPS1 and MPS2. Other transistors MR1, MRS1 are used to read and reset the pixel, respectively. MR2 is present to match MR1 but the gate is always held at VDDHI. MRS2 is used in reset mode to configure the amplifier as a unity gain buffer.