Image sensor with processor controlled integration time

#1. Field of the Invention

#The subject matter disclosed generally relates to the field of semiconductor image sensors.

#2. Background Information

#FIGS. 1 is a schematic of an embodiment of an image sensor;

#FIG. 2 is a schematic of an embodiment of a pixel of the image sensor;

#FIG. 3 is a schematic of an embodiment of a light reader circuit of the image sensor;

#Disclosed is an image sensor that has one or more pixels within a pixel array. The pixels are arranged within a plurality of rows within the array. Each row of the pixel array can be selected by a row decoder in response to an edge of a control signal. The control signal may be one of a plurality of signals generated by a processor coupled to the image sensor. The processor can control the exposure time of the pixels by varying the control signals. The control signals may also have an embedded narrow pulse that is used to determine the location of a “window” in the pixel array.

#The pixel may be a three transistor structure that minimizes the pixel pitch of the image sensor. The entire image sensor is preferably constructed with CMOS fabrication processes and circuits. The CMOS image sensor has the characteristics of being high speed, low power consumption, small pixel pitch and a high SNR.

#Referring to the drawings more particularly by reference numbers, FIG. 1 shows an image sensor 10. The image sensor 10 includes a pixel array 12 that contains a plurality of individual photodetecting pixels 14. The pixels 14 are arranged in a two-dimensional array of rows and columns.