Bonding structure and method of making

#The present invention relates to bonding, and is more particularly related to a bonding structure and method of making.

#In large scale integration, electrical devices such as complementary metal-oxide semiconductor (CMOS) circuitry are fabricated in large quantities on substrates. These substrates can be bonded together using microfabrication techniques to efficiently manufacture micromachined structures. In the case of wafer level packaging, a problem can occur in the hermetic or gas impervious sealed region. Particularly, the bonding process may be lacking in integrity such that the wafers separate one from another. It would be an advantage in the art to provide a good bond between wafers to prevent a breaching of the sealed region there between in wafer level packaged die.

#In the case of thermal ink jet (TIJ) printing, a fluid ejection device, such as a print head, is fabricated to have materials surrounding a firing chamber with underlying thin films. Conductive traces and other structures are also in the print head which is formed into a die in the fabrication process. It would be an advance in the art to provide good adhesion and prevent detachment and/or delamination of the materials surrounding the firing chamber from the underlying thin films, so as to thereby protect conductive traces and other structures in the print head die from ink corrosion.

#A more particular description of the invention is rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. The same numbers are used throughout the drawings to reference like features and components. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

#FIGS. 1a-1b are respective cross-sectional cutaway views, each being an embodiment of the invention depicting a portion of a wafer having fabricated therein a plurality of integrated circuits and that is to be bonded to another wafer using, respectively, a graded stack or a graded dielectric layer, which stack or layer is to be fabricated so as to provide good adhesion to the other wafer;

#FIG. 2 is a cross-sectional cutaway view of an embodiment of the invention depicting a portion of a masked wafer having fabricated therein a plurality of integrated circuits and that is to be bonded to another wafer using a masked layer there on that is being directionally implanted and is to be etched so as to provide good adhesion to the other wafer;

#An embodiment of the invention is an electrical device that includes a pair of substrates that are bonded together by use of a bonding structure. The bonded substrates can optionally be designed to have a sealed region there between. A plurality of integrated circuits are fabricated on one or both of the substrates. The integrated circuits can be exposed to the optional sealed region, either directly or through one or more passageways in fluid communication therewith. The sealed region, which can be a gas impervious region or a hermetically sealed region, prevents ambient gases from outside the substrates from entering into the region. The sealed region is situated between the pair of bonded substrates. In one embodiment of the invention, the sealed region is a substantial vacuum. In another embodiment of the invention, the sealed region can contain an inert gas.

#Embodiments of the present invention provide a proper bond between a pair of substrates that are bonded together by use of a bonding structure wafers so as to provide good adhesion there between. As such, the possibility of a separation of the bonded substrates is decreased. It is desirable to prevent such as separation between the substrates and a breaching of the sealed region there between during or after packaging or dicing because the sealed region, once breached, allows undesirable gas to enter into the sealed region from the ambient. This undesirable gas can cause problems in several ways. The gas entering into the sealed region can cause the pressure inside the sealed region to be other than as designed such that devices of the die that require a high vacuum and/or a low pressure environment will malfunction. For example, a field emission device emits electrons that can collide with gas molecules in an undesirable gas that enters into the sealed region. The collision of the electrons with these gas molecules causes the electrons to scatter or to create ions that can cause damage to the integrated circuits in the die. The gas molecule-electron collisions can also cause the electron beam emitted by the field emission device to be lacking in proper focus. Accordingly, embodiments of the present invention provide a bonding process that increases the integrity such that the substrates are less likely to separate one from another, thereby providing a good bond between substrates so as to prevent a breaching of the sealed region there between, such as in wafer level packaged die.

#Each of the bonded substrates can be a semiconductor substrate. The term “semiconductor substrate” includes semiconductive material. The term is not limited to bulk semiconductive material, such as a silicon wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including but not limited to the semiconductor substrates described above. A substrate may be made of silicon, glass, gallium arsenide, silicon on sapphire (SOS), epitaxial formations, germanium, germanium silicon, diamond, silicon on insulator (SOI) material, selective implantation of oxygen (SIMOX) substrates, and/or like substrate materials. Preferably, the substrate is made of silicon, which is typically single crystalline.