US 2003/0193506 A1Published application

Method and system for more efficiently utilizing processors of a graphics system

AssigneeBroadcom Corporation

InventorsAleksandr M. Movshovich, Brad A. Delanghe, David A. Baer

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Abstract

A method and system for utilizing processor(s) and bypass processor(s) of a computer graphics system are disclosed. The processor(s) and bypass processor(s) render primitives, which are ordered based on their left corners. The method and system include providing a merge circuit, a distributor, a feedback circuit and a controller. The merge circuit determines left and right edges for each primitive. The distributor is coupled with feedback circuit and outputs a first portion of the primitives. The distributor provides a second portion of the primitives to the processor(s) and a third portion of the primitives to the bypass processor(s) if the first portion includes more primitives than there are processor(s). The second portion includes no more primitives than there are processor(s). The feedback circuit, coupled to the merge circuit, re-inputs a fourth portion of the primitives to the bypass processor(s) until the first portion has been rendered for a line.

Claims23

Dependent claims

A system for utilizing at least one processor and at least one bypass processor of a computer graphics system, the at least one processor including a particular number of processors, the at least one processor and the at least one bypass processor for rendering a plurality of primitives, each of the plurality of primitives having a left corner and a right corner, the plurality of primitives being ordered based on the left corner of each of the plurality of primitives, the system comprising:

a merge circuit for determining a left edge for each of the plurality of primitives and determining a right edge for each of the plurality of primitives;
a distributor, coupled with the feedback circuit, for outputting a first portion of the plurality of primitives, the distributor providing a second portion of the plurality of primitives to the at least one processor and providing a third portion of the plurality of primitives to the at least one bypass processor if the first portion of the plurality of primitives includes more primitives than the particular number of processors, the second portion of the plurality of primitives including a number of primitives that is not greater than the particular number of processors,
a feedback circuit, coupled to the merge circuit and the distributor, for re-inputting a fourth portion of the plurality of primitives to the at least one bypass processor until the first portion of the plurality of primitives has been rendered for a particular line;
and
a controller for controlling the feedback circuit, the distributor and the merge circuit.

2 more elements

Dependencies are inferred from the claim text.