Display driving circuit
AssigneeAu Optronics Corporation
InventorsBiing-Der Liu, Jia-Fam Wong, Yao-Jen Hsieh
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AssigneeAu Optronics Corporation
InventorsBiing-Der Liu, Jia-Fam Wong, Yao-Jen Hsieh
Estimating the term…
A display driving circuit. The circuit comprises a data driver outputting a first, second, third and fourth data signal through a data line, a scan driver outputting a first and second scan signal through a first and second scan line, a first, second, third and fourth display cell receiving the first, second, third and fourth data signal through the data line and receiving the first and second scan signal through the first and second scan line, a first switch coupling the first display cell to the data line when the first scan and data signals are asserted, and isolating them from each other when the first scan and second data signals are asserted, and a second switch coupling the third display cell to the data line when the second scan and third data signals are asserted, and isolating them from each other when the second scan and fourth data signals are asserted.
A display driving circuit comprising:
A display driving circuit comprising:
A display driving circuit comprising:
A display driving circuit comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Backward citations are indexed for grants only.
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes: for presentation of an…
Control of matrices with row and column drivers: using an active matrix
Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light…:…
Details of driving circuits: details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related…
Term end not estimated
1. Field of the Invention
The present invention relates to a display driving circuit and particularly to a display driving circuit with fewer data drivers.
2. Description of the Prior Art
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention.
FIG. 1 is a diagram showing a conventional display driving circuit.
FIGS. 2A and 2B are diagrams showing a display driving circuit and signal timing thereof according to a first embodiment of the invention.
FIG. 2A is a diagram showing a display driving circuit 2 according to a first embodiment of the invention. It includes a data driver 21, a scan driver 22, a pixel matrix composed of four (for example) display cells 231˜234, and two switches 241 and 242. The data driver 21 outputs data signals for the display cells 231˜234 through a data line 25. The scan driver 22 outputs scan signals S1 and S2 through scan lines 261 and 262. The display cells 231 and 233 commonly receive the scan signal S1 through the scan line 261, and the display cells 232 and 234 commonly receive the scan signal S2 through the scan line 262. The display cells 231˜234 respectively receive the corresponding data signals commonly through the data line 25. The switches 241 and 242 are respectively coupled between the data line 25 and the display cell 233, and between the data line 25 and the display cell 234.
The display cells 231 and 232 in the odd columns of the pixel matrix are respectively composed of a transistor M21 and a capacitor C21, and a transistor M22 and C22. The transistor M21 and M22 have gates respectively coupled to the scan lines 261 and 262, drains commonly coupled to the data line 25, and sources coupled to the capacitors C21 and C22. The display cells 233 and 234 in the even columns of the pixel matrix are respectively composed of a transistor M23 and a capacitor C23, and a transistor M24 and C24. The transistor M23 and M24 have gates respectively coupled to the scan lines 261 and 262, drains respectively coupled to the switches 241 and 242, and sources coupled to the capacitors C23 and C24. The switches 241 and 242 are transistors M25 and M26 respectively. The transistors M25 and M26 have gates coupled to receive a signal Swing and drains coupled to the data line 25.
FIG. 2B is a diagram showing signal timing of the driving circuit in FIG. 2A.