Display device and interface circuit for the display device

#The present invention relates to a display device such as a liquid crystal display and an interface circuit for the display device.

#FIG. 6 is a diagram showing the structure of a display device such as a liquid crystal display. In FIG. 6, reference numeral 1 denotes a display screen such as a liquid crystal panel, reference numeral 2 denotes a driving circuit 1 such as a scanning line driving circuit, reference numeral 3 denotes a driving circuit 2 such as a signal line driving circuit, reference numeral 4 denotes a control circuit for generating input signals of the scanning line driving circuit 2 and the signal line driving circuit 3, and reference numeral 5 denotes a power source section for generating reference voltages of a circuit system.

#In the structure of the electric circuit of the display device, a signal input from the outside (an input signal in the control circuit 4) includes a clock input signal, a video data input signal, a data enable input signal and other input signals for control (a horizontal synchronizing input signal, a vertical synchronizing input signal and the like). The data enable input signal indicates a valid data period in the video data input signal for a time base, and usually represents a voltage level of H for the valid data period and a voltage level of L for a period other than the valid data period.

#FIG. 1 is a functional block diagram for showing a structure of the circuit of a control circuit or a part of the control circuit in a display device of embodiment 1 of the present invention;

#FIG. 2 is a functional block diagram 1 for showing a structure of the circuit of a control circuit or a part of the control circuit in a display device of embodiment 2 of the present invention;

#FIG. 3 is a functional block diagram 2 for showing a structure of the circuit of a control circuit or a part of the control circuit in a display device of embodiment 2 of the present invention;

#FIG. 1 is a diagram showing, for each functional block, the structure of a control circuit provided in a display device or a part of the control circuit (an interface circuit) according to an EMBODIMENT 1 of the present invention. In FIG. 1, reference numeral 12 denotes a horizontal clock counter for counting a clock number for a valid data period for each horizontal cycle, that is, a circuit section for counting a resolution in a horizontal direction, reference numeral 13 denotes a vertical clock counter for counting a data enable input signal 7 as a clock signal for a valid data period for each vertical cycle, that is, a circuit section for counting a resolution in a vertical direction, reference numeral 14 denotes a horizontal clock count memory for holding a value counted in a last stage for a predetermined period or all the time, reference numeral 15 denotes a vertical clock count memory for holding a value counted in a last stage for a predetermined period or all the time, reference numeral 16 denotes an input signal generating section a driver IC and a driving circuit, reference numeral 17 denotes a horizontal clock count signal indicative of a counted value, reference numeral 18 denotes a vertical clock count signal indicative of a counted value, reference numeral 19 denotes a signal indicative of a counter value holding the horizontal clock count signal 17 for a predetermined period or all the time, reference numeral 20 denotes a signal indicative of a counter value holding the vertical clock count signal 18 for a predetermined period or all the time, reference numeral 21 denotes a plurality of signals input from the outside, and reference numeral 22 denotes a plurality of signals output to the outside which are input to the driver IC and the driving circuit. In some cases, the input signal generating section 16 includes a conventional control circuit or a part of the conventional control circuit.

#First of all, the horizontal synchronizing input signal 6, the data enable input signal 7 and the clock input signal 8 in FIG. 7 are input to the horizontal clock counter 12 in FIG. 1, thereby counting a valid data period for each horizontal cycle up to a value of m by a clock as a unit and outputting a result as the horizontal clock count signal 17. In response to the horizontal clock count signal 17, the horizontal clock count memory 14 holds the value of m for a predetermined period or all the time and outputs the value of m as the horizontal clock count signal 19.

#Similarly, the data enable input signal 7 and the vertical synchronizing signal 11 in FIG. 8 are input to the vertical clock counter 13, thereby counting a valid data period for each vertical cycle up to a value of n in a clock unit and outputting a result as the vertical clock count signal 18. In response to the vertical clock count signal 18, the vertical clock count memory 15 holds the value of n for a predetermined period or all the time and outputs the value of n as the vertical clock count signal 20.