Low power consumption pipelined analog-to-digital converter

A pipelined analog-to-digital converter for receiving an external analog signal, and converting the analog signal via a plurality of pipelined stage circuits to output a digital signal in responsive to the analog signal;

• the stage circuit comprising an amplifier, a comparator, a first compensator and a second compensator for converting the inputted analog signal via a sampling mode, a first amplifying mode and a second amplifying mode;
• in the sampling mode, the amplifier being inputted with an analog input signal, the comparator comparing the analog input signal with a reference signal, and then generating a first digital output code;
• in the first amplifying mode, the first compensator selectively adding a first compensation value to the analog input signal according to the first digital output code, and then generating a first input signal, the amplifier amplifying the first input signal and then generating a first output signal, the comparator comparing the first output signal with the reference signal and then generating a second digital output code;
• in the second amplifying mode, the first compensator selectively adding a second compensation value to the analog input signal according to the first digital output code and the second digital output code, and then generating a second input signal;
• the amplifier amplifying the second input signal and then generating a second output signal, the second compensator selectively choosing a third compensation value according to the first digital output code and the second digital output code, and the third compensation value being amplified and added to the second output signal to generate an analog output signal sent to the next stage circuit.

A method of converting an analog signal to a digital signal, the converting method receiving the external analog signal in a pipelined analog-to-digital converter and converting the analog signal via a plurality of pipelined stage circuits to output the corresponding digital signal, the converting method comprising:

• receiving an analog input signal in one of the plurality of stage circuits;
• comparing the analog input signal with a reference signal to generate a first digital output code;
• adding selectively a first compensation value, according to the first digital output code, to the analog input signal to generate the first input signal;
• amplifying a first input signal to generate a first output signal;
• comparing the first output signal with the reference signal to generate a second digital output code;
• adding selectively a second compensation value, according to the first digital output code and the second digital output code, to the analog input signal to generate a second input signal;
• amplifying the second input signal to generate a second output signal;
• choosing a third compensation value according to the first digital output code and the second digital output code, and amplifying and adding the third compensation value to the second output signal to generate an analog output signal;
• and
• transmitting the analog output signal to the adjacent next stage circuit.

A converting method for converting an analog signal to a predetermined (2n−1) digital output codes (b1, b2 . . . b2n−1) in a pipelined analog-to-digital converter having a predetermined (n) series stage circuits, the converting method comprising:

• executing the following steps in a stage circuit Si wherein i is a natural number from 1 to (n−1):
• I. receiving an analog input signal Vin(i) and comparing with a predetermined reference signal to generate a first digital output code b2i−1;
• II. subjecting the analog input signal Vin(i) to a sample and hold operation, to an amplification by two, and to add selectively, according to the first digital output code b2i−1, a first compensation value as to generate a first output signal Vout1(i);
• III. comparing the first output signal Vout1(i) with the reference signal as to generate a second digital output code b2i;
• IV. subjecting the analog input signal Vin(i) to a sample and hold operation, to an amplification by four, and to add selectively, according to the first digital output code b2i−1 and the second output code b2i, a second compensation value as to generate a second output signal Vout2(i);
• V. adding selectively a third compensation value, according to the first digital output code b2i−1 and the second output code b2i, to the second output signal Vout2(i) as to generate an analog output signal Vout(i);
• and
• VI. transmitting the analog output signal Vout(i) to the adjacent next stage circuit Si+1 to serve as an analog input signal of the next stage circuit Si+1;
• repeating the Step (1) to Step (6) from the first stage circuit S1 to the (n−1)-th stage circuit Sn−1 to generate the (2n−2) digital output codes (b1, b2, . . . b2n−2);
• and
• in the n-th stage circuit Sn, receiving the analog output signal Vout(n−1) of the (n−1)-th stage circuit Sn−1 to serve as the analog input signal Vin(n) of the n-th stage circuit Sn, and comparing the analog input signal Vin(n) with the reference signal to generate the digital output code b2n−1.