Serial-to-parallel data converter and method of conversion

#1. Field of Invention

#The invention generally relates to a data converter and the method of conversion. More specifically, the invention relates to a serial-to-parallel data conversion circuitry that has an additional pre-register installed in a multi-phase clock architecture to maintain the number of required phase clock signals as same as the number of the width of the parallel data bits.

#2. Related Art

#The present invention will become more fully understood from the detailed description given hereinbelow illustration only, and thus are not limitative of the present invention, and wherein:

#FIG. 1 is a conventional latch circuit diagram for serial-to-parallel data conversions.

#FIG. 2 is a conventional latch circuit diagram for serial-to-parallel data conversions in a multi-clock phase architecture.

#The disclosed serial-to-parallel data conversion method converts a serial data into a n-bit parallel data for output. The method includes the steps of: generating n phase clock signals corresponding to the n-bit parallel data in a conversion cycle, within which the serial data is converted into the n-bit parallel data; using the n phase clock signals to convert the serial data into n-bit first parallel data and second parallel data within the conversion cycle; and selecting one from the first parallel data and second parallel data as the parallel data for output and the other for serial data conversions. In particular, the corresponding bit data in the first parallel data and the second parallel data refer to the same phase clock signal to latch the serial data. Therefore, the serial-to-parallel data conversion does not need to refer to 2n phase clock signals.

#With reference to FIG. 3, a 5-bit parallel data conversion is employed to explain a preferred embodiment of the present invention. The conversion of the serial data into 5-bit parallel data for output has to generate 5 phase clocks Phase—0, Phase—1, Phase—2, Phase—3, and Phase—4 corresponding to the parallel data in a conversion cycle. This can be implemented using a phase clock generator. These phase clocks refer to a work clock CLK to have a rising edge of the clock in order within a conversion cycle. The first parallel data and the second parallel data simultaneously refer to the 5 phase clocks in order to latch the serial data in order. That is, each corresponding bit datum of the first parallel data and the second parallel data refers to the same phase clock signal to latch the serial data. During different conversion cycles T1 and T2, one of the first parallel data and the second parallel are selected as the output parallel data and the other for serial data conversion. For example, if the first parallel data are selected as the output data during the conversion cycle T1, the input serial data is converted into the second parallel data; whereas when the second parallel data are selected as the output data during the conversion cycle T2, the input serial data is converted into the first parallel data. This alternating method allows the following device enough time to catch the latched parallel data during the conversion cycle.

#With reference to FIG. 4, in this embodiment a serial-to-parallel data converter is described in accord with the above disclosed serial-to-parallel data conversion method of the present invention. The multi-clock phase architecture comprises a phase clock generator (not shown in the drawing) for generating 5 phase clocks. These 5 phase clocks simultaneously drive a first data receiver 10 and a second data receiver 20. Each data receiver is comprised of a latch circuit 11, 21. The latch circuit is a D-type flip-flop (FF) with an enable signal. The output Q of such a FF remains invariant when the enable signal CE is at a low level L. In the first data receiver 10 and the second data receiver 20, the D-type FF for storing the corresponding bit of parallel data refer to the same phase clock. For example, the D-type FF 11 of the first data receiver 10 and the D-type FF 21 of the second data receiver 20 store the first bit of parallel data and driven by the same phase clock Phase—1.