Clock and data recovery with a feedback loop to adjust the slice level of an input sampling circuit

A method comprising:

• receiving a stream of incoming data signals;
• generating re-timed data bits corresponding to the incoming data signals;
• providing an offset cancellation signal to cancel amplitude offset from signals in the stream;
• and
• adjusting a magnitude of the offset cancellation signal based on a state of a transition bit occurring between re-timed data bits.

A method comprising:

• sampling a pair of consecutive data bits and an intervening transition bit from a stream of incoming data signals using an input sampling circuit;
• determining whether a slice level of the input sampling circuit should be incremented or decremented based on the sampled bits;
• repeatedly performing said sampling and said determining for other groups of data and transition bits;
• adjusting the slice level based on repeated performances of said determining;
• and
• generating re-timed data signals corresponding to the incoming data stream.

An apparatus comprising:

• an input to receive a stream of incoming data signals;
• a timing acquisition circuit including a sampling circuit to sample the incoming data signals, said timing acquisition circuit to extract clock information from the incoming data signals and to provide re-timed signals corresponding to the incoming data signals based on the extracted clock information;
• and
• circuitry coupled between an output of the timing acquisition circuit and said input to adjust a slice level of the sampling circuit based on a transition bit sampled from the stream.

An apparatus comprising:

• an input to receive a stream of incoming data signals;
• an amplifier to amplify the incoming data signals;
• a timing acquisition circuit including a phase detector and a sampling circuit, the timing acquisition circuit coupled to an output of the amplifier to extract clock information from the amplified incoming data signals and to provide re-timed signals corresponding to the incoming data signals based on the extracted clock information;
• and
• circuitry coupled between an output of the timing acquisition circuit and an input of the amplifier to adjust the slice level of the sampling circuit based on a transition bit in the stream.

An apparatus comprising:

• an input to receive a stream of incoming data signals;
• a timing acquisition circuit coupled to said input and including a sampling circuit to sample the incoming data signals, said timing acquisition circuit to extract clock information from the incoming data signals and to provide re-timed signals corresponding to the incoming data signals based on the extracted clock information;
• and
• a feedback loop coupled between an output of the timing acquisition circuit and said input to adjust a slice level of the sampling circuit based on a transition bit sampled from the stream.