Phase locked loop input receiver design with delay matching feature

#As shown in FIG. 1, a typical computer system 10 has, among other components, a microprocessor 12, one or more forms of memory 14, integrated circuits 16 having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths 19, e.g., wires, buses, etc., to accomplish the various tasks of the computer system 10.

#In order to properly accomplish such tasks, the computer system 10 relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator 18 generates a system clock signal (referred to and known in the art as “reference clock” and shown in FIG. 1 as SYS_CLK) to various parts of the computer system 10. Modern microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock, and thus, it becomes important to ensure that operations involving the microprocessor 12 and the other components of the computer system 10 use a proper and accurate reference of time.

#One component used within the computer system 10 to ensure a proper reference of time among a system clock and a microprocessor clock, i.e., “chip clock,” is a type of clock generator known as a phase locked loop, or “PLL” 20. The PLL 20 is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to a reference signal. Referring to FIG. 1, the PLL 20 has as its input the system clock, which is its reference signal, and outputs a chip clock signal (shown in FIG. 1 as CHIP_CLK) to the microprocessor 12. The system clock and chip clock have a specific phase and frequency relationship controlled by the PLL 20. This relationship between the phases and frequencies of the system clock and chip clock ensures that the various components within the microprocessor 12 use a controlled and accounted for reference of time. When this relationship is not maintained by the PLL 20, however, the operations within the computer system 10 become non-deterministic.

#FIG. 1 shows a typical computer system.

#FIG. 2 shows a block diagram of a typical phase locked loop.

#FIG. 3a shows a circuit diagram of a phase locked loop.

#FIG. 3a shows a diagram of a PLL 201. The PLL 201 has an input of system clock 41 that is used to create a phased output, output clock 342. The basic elements of the PLL core 36 are a phase-frequency detector 302, charge pump 304, loop filter 306, and voltage-controlled oscillator 308. Output clock 342 may have a higher frequency than the system clock 41. A divide-by-N circuit 39 is used to reduce the frequency of the output clock 342 so that the system clock 41 and divided output clock 340 can be input to the phase-frequency detector 302. The phase-frequency detector 302 measures the phase and frequency difference between system clock 41 and divided output clock 340. The phase-frequency detector 302 produces signals that control a charge pump 304, typically up or down pulses (not shown), to increase or decease the net charge at the output of the charge pump 304. The charge pump 304 adds or removes charge from the loop filter 306. The loop filter 306 may be composed of a resistor and capacitor in series that are connected to ground. The charge pump 304 adjusts the voltage stored on the capacitor in the loop filter 306. The voltage-controlled oscillator 308 produces the output clock 342 that has a frequency proportional to the voltage input to the voltage-controlled oscillator 308. Because the voltage input to the voltage-controlled oscillator 308 may be susceptible to power supply noise, the output clock 342 may jitter.

#In FIG. 3b, the frequency response of the PLL 220 may be analyzed with a Laplace transform approximation, where the sample operation of the phase-frequency detector is ignored. This approximation is useful for loop bandwidths about a decade or more below the operating frequency of the PLL. This loop bandwidth constraint is also required for stability due to the reduced phase margin near the higher order poles that result from the delay around the sampled feedback loop. The modeled charge pump 230 adds or removes charge to its output depending on the state of input control signals, typically up or down pulses (not shown). Both pulses may be ‘on’ at the same time, however, if the up or the down pulse remains ‘on’ longer than the other, the net charge at the output of the charge pump 230 increases or decreases. The charge pump gain may be modeled as a linear gain versus phase error where IOUT(s)/ΦE(s)=ICP/2π. The loop filter 232 may be modeled as a series combination of a capacitor, C, and a resistor, R, connected from IOUT to ground. The loop filter 232 transforms the output of the charge pump, IOUT, into the voltage-controlled oscillator input voltage, VFILT. The Laplace transform of the series resistor and capacitor in the loop filter 232 is VFILT(s)/IOUT(s)=(sRC+1)/(sC). The transfer function of the capacitor and resistor shows that a zero is added that adds stability to the PLL loop. The voltage-controlled oscillator 234 outputs a clock that has a frequency proportional to the input voltage VFILT. The Laplace transform of the voltage-controlled oscillator 234 is ΦOUT(s)/VFILT(s)=ICP/VFILT(s)=KVCO/s. The closed-loop transfer function can now be derived as H(s)=ΦOUT(s)/ΦIN(s)=[(R KVCO ICP/2π)/(s+1/R C)]/[s2+s R C KVCO ICP/2πN C+KVCO ICP/2N C]. H(s) is a second order system that has one pole from the loop filter 232 and one pole from the voltage-controlled oscillator 234, and one zero from the resistor, R, in the loop filter 232. The transfer function H(s) has a natural frequency ωn=(KVCO ICP/2πN C)0.5 and a damping factor ζ=R C ωn/2.

#The loop bandwidth is defined as the frequency at which the output magnitude is 3 dB lower than when the input is DC. Loop bandwidth is not the same as natural frequency, although they are often close. Once ζ, ωn, KVCO, and ICP are chosen, the values for R and C can be determined for any selected loop bandwidth. Low loop bandwidth allows the PLL to filter input jitter. High loop bandwidth allows the PLL to follow and compensate for output error induced by power supply noise. Thus, a design tradeoff must be made in the loop bandwidth of the PLL. The value for C has a large effect on loop bandwidth and natural frequency. Optimizing the PLL loop bandwidth relates to balancing the effect and treatment of input error with the PLL loop's speed of response to compensate for output error induced by power supply noise.