PLL for clock recovery with initialization sequence
AssigneeFairchild Semiconductor Corporation
InventorsJames J. McDonald II, Ronald B. Hulfachor, Jim Wunderlich
Life of this patent
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Abstract
A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.
Claims16
A system for generating de-serializing timing signals for a serial bit stream word of M bits including data and framing bits, the system comprising:
- a voltage controlled oscillator with a number of outputs equal to M, wherein the outputs are equally offset from each other in phase over the period of about M bits, wherein each phase in succession about matches the corresponding successive bits in the bit stream,
- a phase detector arranged to receive the serial bit stream word and a phase output from the voltage controlled oscillator, wherein the phase detector compares the serial bit stream word to the voltage controlled oscillator phase output,
- a control signal output from the phase detector, wherein the control signal indicates whether the voltage control oscillator phase output must go faster or slower, and wherein the voltage controlled oscillator output, in response to the control signal, becomes phase locked to the serial bit stream word,
- a reset signal input to the phase detector, wherein when the reset signal is true the control signal is disabled and when the rest signal is false the control signal is enabled,
- circuitry receiving a combination of voltage controlled oscillator phase outputs and logically forming the reset signal therefrom, wherein the reset signal is false for the last of the M bits to the beginning of the second of the M bits, thereby defining a time window where the control signal is active.
A method for generating de-serializing timing signals for a serial bit stream word of M bits including data and framing bits, the method comprising the steps of:
- providing a voltage controlled oscillator outputting a number of phase outputs equal to M, wherein the outputs are equally offset from each other in phase over the period of about M bits, wherein each phase in succession about matches the corresponding successive bits in the bit stream,
- phase comparing the serial bit stream word and a phase output,
- producing a control signal output from the phase comparing, wherein the control signal indicates whether the oscillator must go faster or slower, and wherein the oscillator output in response to the control signal becomes phase locked the serial bit stream word,
- opening a time window during which the control signal is enabled, and when the control signal is disabled the oscillator output is not responsive to the control signal,
- combining phase outputs and logically forming the time window therefrom, wherein the time window is open for the last of the M bits to the beginning of the second of the M bits of the serial bit word.
Dependencies are inferred from the claim text.