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AssigneeThe Regents of the University of California
InventorsLarry Larson, Chengzhou Wang
Estimating the term…
To an existing class AB amplifier receiving at a gate of one of a NMOS or a PMOS type CMOS transistor an input signal, the gate of this CMOS transistor having a nonlinear gate capacitance with its switched operation, is added another, opposite-type, one of a NMOS or a PMOS type CMOS transistor that also receives at its gate the same input signal. The nonlinear gate capacitance of this other CMOS transistor is essentially opposite to the nonlinear gate capacitance of the existing CMOS transistor that receives the input signal within the class AB amplifier. This other transistor serves to compensate for the nonlinear gate capacitance of the existing CMOS transistor. Any nonlinearity due, in particular, to any nonlinear change in gate capacitance of a CMOS transistor that is used in particular within a class AB amplifier is thus substantially canceled.
An improved class AB amplifier comprising:
A method of compensating a non-linear gate capacitance at the gate of NMOS- or a PMOS-type CMOS transistor of a class AB amplifier, the method comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
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Using predistortion circuits: using the nonlinearity inherent to components, e.g. a diode
Modifications of amplifiers to reduce non-linear distortion: in field-effect transistor amplifiers
Amplifiers
Term end not estimated
1. Field of the Invention
The present invention generally concerns CMOS power amplifiers, particularly as are operated class AB.
The present invention particularly concerns CMOS power amplifier circuit design, particularly as operated class AB and particularly as employ an NMOS input transistor, canceling at least one circuit nonlinearity.
Referring particularly to the drawings for the purpose of illustration only and not to limit the scope of the invention in any way, these illustrations follow:
FIG. 1 is a prior art schematic of an equivalent circuit of a NMOS CMOS transistor modeling the nonlinear gate capacitance of the transistor.
FIG. 2 is a prior art graph of simulation with the SPICE program of the equivalent circuit of FIG. 1 with W=2.6 mm and L9=0.6 μm.
The following description is of the best mode presently contemplated for the carrying out of the invention. This description is made for the purpose of illustrating the general principles of the invention, and is not to be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
Although specific embodiments of the invention will now be described with reference to the drawings, it should be understood that such embodiments are by way of example only and are merely illustrative of but a small number of the many possible specific embodiments to which the principles of the invention may be applied. Various changes and modifications obvious to one skilled in the art to which the invention pertains are deemed to be within the spirit, scope and contemplation of the invention as further defined in the appended claims.
Of the two major sources—discussed in the Background of the Invention section of this specification—of nonlinearity in the class AB operation of a CMOS power amplifier, nonlinear input capacitance is illustrated in the NMOS CMOS input power transistor equivalent circuit of FIG. 1. When the transistor turns on and off during Class AB operation, the gate capacitance Cgs also changes dramatically. This varying capacitance causes nonlinearity at the gate of the transistor. In other words the gate voltage signal Out will be a nonlinear version of the input signal In because of this capacitance.