Zero-bias bypass switching circuit using mismatched 90 degrees hybrid

#This invention is generally directed to the function of providing an RF bypass function for tower-mounted low noise amplifiers (LNAs).

#The present invention is directed to the operation of amplifiers, such as low noise amplifiers in a tower-mounted active antenna system, such as an antenna system used in a base station for wireless communications. Generally speaking, such base stations employ a number of amplifiers, including low noise amplifiers (LNAs). In the case of active antenna systems, the LNAs are mounted on the tower adjacent to the radiating elements or antennas. On the signal receive side of such an installation, a low noise amplifier is typically employed at the tower top for improving the signal-to-noise ratio of the received signal and providing an amplified signal to other base station equipment, which may also be tower mounted, but which is more typically mounted in a base station enclosure at the base of the tower. Failure of tower-mounted equipment presents certain maintenance issues. Since access to the tower mounted equipment requires a worker to actually climb the tower, it is considered desirable to arrange for various fail-safe devices or modes of operation of the tower mounted equipment, including the LNAs.

#One such fail-safe mode of operation for a tower-mounted LNA is an automatic bypass capability for bypassing the low noise amplifier (LNA) when a failure mode of the amplifier is detected. Such a failure mode in the LNA results in a significant degradation of the signal output by the LNA. A failure may occur, for example, due to the loss of DC bias current supplied to the tower mounted equipment, which might occur for a number of reasons. In cases of a defined failure mode of the LNA, the LNA may be automatically or otherwise bypassed, feeding the received signals directly from the antenna to the base station equipment, typically at the enclosure at the base of the tower. While such a bypass may degrade the signal-to-noise ratio somewhat in the absence of the amplifier, it is usually considered preferable to the signal degradation, which takes place when the amplifier is in a failure mode. Therefore, it is desirable to provide a bypass arrangement, to bypass an LNA, which is in a predefined failure mode from the absence of a DC control bias.

#The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with a general description of the invention given below, serve to explain the principles of the invention.

#FIG. 1 is a schematic of a zero-bias bypass switching circuit in accordance with one embodiment of the invention.

#FIG. 2 is a schematic of a zero-bias bypass switching circuit in accordance with another embodiment of the invention.

#To address the objectives noted above and other objectives in the art, the invention provides a bypass capability that is low-loss, and relatively inexpensive. The solid-state design is also compact and robust.

#Using PIN diodes with low “zero voltage” capacitance, a bypass switch design is possible which achieves the desired goals. Insertion loss of the switch is no more than approximately 0.5 dB total (0.25 dB for each section) in the “through” path, and the switch has at least around 25 dB isolation between alternate paths. This design has loss in the normal “through” path comparable to far more expensive relays. It is a solid-state design with no mechanical components. In another embodiment of the invention, shown in FIG. 2, a further improvement of insertion loss and isolation is realized.

#Referring to FIG. 1, one embodiment of a zero-bias bypass switching circuit or switch in accordance with the invention is illustrated in circuit schematic form. In one embodiment, the switch or switching device includes a bypass circuit portion 10, which in the illustrated embodiment comprises a pair of series-coupled quarter wavelength lines 12, 14 that are coupled between an input 16 and an output 18 of the circuit. In the illustrated embodiment, the two-quarter wave lines 12 and 14 are coupled in series by a DC blocking capacitor 20.