Biasing system and method for low voltage DC-DC converters with built-in N-FETs

#The present invention relates to multiple-output low-voltage DC-DC converters with integrated power MOSFETs. Specifically, the present invention is a new gate drive supply circuit for driving high-side and low-side N-type MOSFETs.

#Modern portable electronic devices such as digital cameras and digital video camcorders require a myriad of different power sources for their operation. For example, 2.5 volts may be required for the dynamic RAMS in these devices, 1.2 to 1.8 volts is required for an on-board microprocessor, while 5.0 volts is required for the analog circuitry and the USB interface. Other voltages are required to run various motors such as the zoom lens motor of a camera or the tape transport motor in the VCR part of the camcorder. Each of these devices however is powered by a set of batteries, usually, Lithium Ion batteries, that supply a voltage in the range of about 2.7 volts to 4.2 volt. In addition, it is common to back-up the Lithium Ion battery with 2-cell Alkaline batteries, causing the input supply to have a range of about 2.0 to 5 volts. To deliver these different voltages to the various subsystems in these portable electronic devices from a battery source having a wide input range, requires a complete power system in the portable device. Once such power system comprises a several dc-to-dc converters to convert the battery voltage to the required subsystem voltage.

#Existing dc-to-dc power converters typically employ a switching regulator to create a desired voltage. One such converter is a step-down converter in which the switching transistors are a complementary pair, nMOS and pMOS, of power FETs. The P-FET transistor is used for the high side switching transistor and the N-FET transistor is used for the low side switching transistor. The use of the P-FET transistor is a disadvantage because pMOS transistors have higher on resistance (rDS) than nMOS transistors having the same physical dimensions (W/L). The higher on-resistance occurs in an pMOS device because resistance of a MOS transistor channel is inversely proportional to the mobility of the carriers in the channel, which is lower (about ½) for pMOS transistors compared to NMOS transistors. Higher on-resistance on a switching transistor reduces the efficiency of the power conversion due to heating losses in the transistor. Also, as the battery voltage drops below 2.5 volts it becomes more difficult to fully turn on a pMOS device used in the high side of the conversion switch, because the high side P-FET requires at least 3 to 5 volts to operate properly. This restricts the range of operation for prior art down converters to 3 to 5 volts.

#These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:

#FIG. 1 shows a prior-art buck DC-DC converter using a pair of P-FET and-N-FET as high-side and low-side switches, respectively;

#FIG. 2 shows a prior-art buck DC-DC converter using a pair of N-FETs as high-side and low-side switches wherein a boot-strap circuit is used to drive the high-side switch;

#FIG. 1 shows a prior art buck converter using a P-FET as the high-side switch and an N-FET as the low side switch. Input voltage VIN 11 is connected to the source terminal of the PFET 12. VIN 11 also supplies the operating VDD voltage for internal control circuit, including high-side gate driver 14, low-side gate driver 15, a Tf delay circuit 16, a Tr delay circuit 17, a set-reset (SR) flip-flop 18, a bandgap reference generator 19, a clock and ramp generator 20, a comparator 21, and an error amplifier 23.

#One input of the error amplifier 21 is connected to the output of the bandgap reference generator 19, the other input of the error amplifier 21 is made available for connecting to the regulated output voltage 26. The output of the error amplifier 21 is connected to negative input of comparator 21, which has its positive input connected to the output of the clock and ramp generator 20, which also drives the set input of the SR flip-flip 18. The output of the comparator 21, is connected to the reset input of the SR flip-flop 18. The negative output (Qn) of the SR flip-flop is connected to Tf delay circuit input 16 and Tr delay circuit input 17, whose outputs connect, respectively, to the input of the high-side driver 14 and the input of the low-side driver 15. The output of the high-side driver drives the gate of the power P-FET and the output of the low-side driver drives the gate of the power N-FET. The junction between the P-FET and the N-FET, LX, is made available to connect to one node of the energy storage inductor 25, whose other node provides the output voltage VO 26. Typically, a filter capacitor 27 is also connected to the output voltage VO. 26.

#In operation, to turn on P-FET 12, gate driver 14 pulls the gate of P-FET 14 to ground, providing a source to gate voltage about equal to VIN, the supply voltage 11. To turn off P-FET 12, the gate driver 14 pulls the gate of P-FET 14 to approximately VIN 11, providing a gate-to-source voltage of about zero volts.