Sequencing circuit for applying a highest voltage source to a chip

#The present invention relates generally to power supply circuitry and more particularly, relates to a sequencing circuit for applying a highest voltage source to a chip.

#In known electronic systems, various DC voltage levels often are required that may be provided by multiple different DC supplies. For example, one chip may have a voltage power rail Vdd connected to a 5 volt power supply and include components and input/output (I/O) that use a 3.3 volt power supply. Typically, a system power supply does not instantly provide the correct supply voltages during startup or power down of an electronic system, such as a computer system. Known power supplies have a startup delay when the system is powered on and also a bring down delay when the when the system is powered off.

#A sequencing problem exists with some chips included in such known electronic systems. For example, one chip has a voltage power rail Vdd connected to the +5 volts of the system, and this chip also used 3.3 volts and had I/O pins that were also pulled up or wired to other chips that also used the 3.3 volt supply. This chip would latch up if at any time the voltage power rail Vdd is less than any other voltage that was used by this chip. This sequencing problem required that the voltage power rail Vdd be maintained as the highest voltage to the chip during power up and power down of the system.

#The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:

#The single drawing figure is a schematic and block diagram representation of a sequencing circuit in accordance with the preferred embodiment.

#Having reference now to the drawings, there is shown an exemplary sequencing circuit in accordance with the preferred embodiment generally designated by the reference character 100. Sequencing circuit 100 satisfies the requirement that a chip power supply input labeled Vdd is the highest voltage to a chip 120 at any time. Sequencing circuit 100 connects the chip power supply input Vdd to the highest of the two voltages that the chip 120 receives or has on a chip input/output (I/O).

#Sequencing circuit 100 includes a first transistor 102 coupled between a first system power supply labeled VOLTAGE SUPPLY 1 (3.3V) and the chip power supply input VDD to the chip 120 and a second transistor 104 coupled between a second system power supply labeled VOLTAGE SUPPLY 2 (5V) and the power supply input VDD to the chip 120. The first transistor 102 and second transistor 104 of the preferred embodiment are field effect transistors (FETs), such as metal oxide semiconductor FETs (MOSFETs).

#Sequencing circuit 100 includes a comparator 106 for sensing a highest voltage of the first and second system power supplies. A first biasing resistor 108 is coupled between a non-inverting input of the comparator 106 and the first system power supply VOLTAGE SUPPLY 1. A second biasing resistor 110 is coupled between an inverting input of the comparator 106 and the second system power supply VOLTAGE SUPPLY 2. Sequencing circuit 100 includes two bias voltages labeled +5 VCS and +12 VCS. A third biasing resistor 112 is coupled between the reference or bias voltage source +5 VCS and an output of the comparator 106. The first transistor 102 and second transistor 104 have a gate input operatively controlled by the comparator 106. An output of the comparator 106 is applied to the gate of the first transistor 102. A third transistor 114 includes a gate connected to the output of the comparator 106. The source and drain of the third transistor 114 are connected between a biasing resistor 116 connected to the reference supply 12 VCS and the second system power supply VOLTAGE SUPPLY 2. The second transistor 104 has its gate input operatively controlled by the comparator 106 via the third transistor 114.