Semiconductor memory delay circuit

#This U.S. nonprovisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2002-19951, filed on Apr. 12, 2002, the entire contents of which are hereby incorporated herein by reference.

#The present invention generally relates to semiconductor memories and, in particular, to semiconductor memories employing delay circuits.

#Semiconductor memories may control internal circuits thereof by way of signals having various operation timings. Delay circuits may be employed along signal propagation paths in order to establish such various signal operation timings. In particular, high-frequency memories, such as DRAMs, SRAMs, and flash memories, may utilize address transition detection (ATD) circuits to access memory core circuits, such as sense amplifiers and memory cells, in response to address transitions.

#Exemplary embodiments of the present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

#FIG. 1 illustrates a conventional general flash memory.

#FIG. 2 illustrates a conventional delay circuit.

#It should be understood that the following description of the exemplary embodiments is merely illustrative and should not be considered as limiting of the claimed invention.

#In the following detailed description, specific details are set forth in order to provide a thorough understanding of the exemplary embodiments of the present invention. It will be obvious, however, to one skilled in the art that the exemplary embodiments of the present invention may be practiced without these specific details

#FIG. 4 illustrates a circuit diagram of a delay circuit according to an exemplary embodiment of the present invention. Such a delay circuit as illustrated in FIG. 4 may be used in general flash memories. For example, the delay circuits according to the exemplary embodiments of the present invention may be used with a general flash memory as illustrated in FIG. 1. However, the exemplary embodiments may be implemented in other circuit arrangements as design requires.