Precision-controlled duty cycle clock circuit

#This Application is a continuation of U.S. patent application Ser. No. 09/480,811, filed on Jan. 10, 2000, the entire disclosure of which is incorporated herein by reference.

#1. Field of the Invention

#The invention relates to the field of precision-controlled duty cycle clock circuits for use with electronic devices. More specifically, the invention provides a circuit having an adaptive adjustment to improve the controllability of the duty cycle of an output clock signal in response to the changing characteristics of an input clock signal. The invention finds application in a variety of electronic devices, including wireless communications devices.

#The present invention will be apparent to those skilled in the art upon reading the following description in view of the accompanying drawings, wherein:

#FIG. 1 is a block diagram of a clock signal duty cycle controller coupled between an input clock source and a clocked digital circuit;

#FIG. 2 illustrates a preferred output clock signal generated by the clock signal duty cycle controller of FIG. 1;

#Turning now to the drawing figures, FIG. 1 sets forth a block diagram of a clock signal duty cycle controller 300 coupled between an input clock source 100 and a clocked digital circuit 200. As shown in this figure, the input clock source 100 transmits a first clock signal 102, preferably a curvilinear signal, to a clock signal utilizing device 200, preferably a clocked digital circuit, via the clock signal duty cycle controller 300. The first clock signal 102 generated by the clock source 100 and placed on path 104 may be poorly conditioned due to unknown DC offsets, unknown amplitudes or an asymmetrical waveform. In contrast, a second clock signal 106 output from the clock signal duty cycle controller 300, preferably a square-wave clock signal, has an accurately controlled duty cycle and adjusts to changes in characteristics of the clock source 100. The second clock signal 106 is placed on path 108 to be used as the clocking signal for the clocked digital circuit 200.

#FIG. 2 illustrates a preferred output clock signal 106 generated by the clock signal duty cycle controller 300. In one clock period (tperiod), the clock signal 106 includes a high phase signal component (measured in time by tH), a low phase signal component (measured in time by tL), and an uncertainty component (measured in time by tX) Preferably, the clocked digital circuit 200 performs logic processes during both the high phase (tH) 110 and the low phase (tL) 112 of the clock signal 106. Minimizing the uncertainty phase (tX) 114 permits optimization of the duty cycle (tH/tL) of the clock signal 106.

#By maximizing tH and tL, the digital circuit 200 can operate at higher clock speeds, it can operate at a lower supply voltage, it can operate at extreme temperatures, or some combination of these parameters. The clock speed, supply voltage, and temperature determine the propagation delay of the digital circuit 200.