Frequency divider system

#This invention relates generally to frequency division techniques for RF (Radio Frequency) signals. More particularly, the present invention relates to a circuit for converting a system clock signal to a clock signal having a reduced frequency.

#Most electronic devices require a clock signal to synchronize operations of its internal components with each other. This clock signal is commonly referred to as the system clock, and can be provided by a crystal oscillator having a fixed frequency. Telecommunication devices also require clock signals for transmission and reception of RF signals in addition to a system clock.

#Advances in circuit design and semiconductor manufacturing techniques have increased the maximum operating frequency of high performance electronic devices. For example, current Intel Pentium class microprocessors can run at a system clock frequency between 1 GHz and 2 GHz.

#Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:

#FIG. 1 shows a block diagram of an RF divider system according to an embodiment of the present invention;

#FIG. 2 shows a block diagram of the divide-by-3 circuit block shown in FIG. 1;

#A frequency divider circuit for providing a divided clock signal having a frequency that is a factor less than the frequency of an incoming system clock signal is disclosed. The frequency divider includes a clock generator circuit coupled to a delay circuit that operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a number of system clock transitions after the divided clock signal is driven to the first logic state. In the reset phase, the first two flip flops are reset only, the delay formed by the second two flip-flops does not have any reset inputs, however, their inputs are reset to a logic ‘0’ two clock cycles after the reset signal is asserted. The delay circuit therefore maintains a 50% duty cycle for the divided clock signal. More particularly, the frequency divider according to embodiments of the present invention provides a clock signal that is divided by three, or any other odd divisions such as divide by (2*n+1) where n>=0 while maintaining a 50% duty cycle for the divided clock signal.

#FIG. 1 is a block diagram of an RF divider system suitable for portable wireless devices. The RF divider system 100 receives a system clock signal CLK and can selectively provide a divide-by-1, 2 or 3 clock signal. Additionally, RF divider system 100 conserves power by activating only the selected clock divider sub-circuit. RF divider system 100 includes a divide-by-3 sub-block, a divide-by-2 sub-block, a divide-by-i sub-block, a decoder 102 and a bias circuit 104.

#The divide-by-3 sub-block consists of a clock input buffer 106, a divide-by-3 circuit 108 and clock output buffer 110. The clock input buffer 106 receives the system clock CLK and provides a buffered CLK signal to the divide-by-3 circuit 108. The divide-by-3 circuit 108 generates a pre-buffered divided system clock signal having a frequency equal to the system clock frequency divided by 3. The pre-buffered divided system clock signal is buffered by clock output buffer 110 and appears on the o3 output terminal.