Dynamic to Static converter with noise suppression

#1. Field of the Invention

#This invention is related to the field of dynamic and static logic circuits, and more particularly to noise issues in dynamic to static conversion.

#2. Description of the Related Art

#The following detailed description makes reference to the accompanying drawings, which are now briefly described.

#FIG. 1 is a circuit diagram of a prior art dynamic circuit with dynamic to static conversion.

#FIG. 2 is a circuit diagram of one embodiment of dynamic circuitry and dynamic to static conversion circuits.

#While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

#Turning now to FIG. 2, a circuit diagram illustrating one embodiment of dynamic circuitry, dynamic to static converter circuits, static logic circuitry, and a static storage device is shown. Other embodiments are possible and contemplated. More particularly, the embodiment of FIG. 2 includes a set of A-phase dynamic logic circuits 30A-30D, a set of B-phase dynamic logic circuits 32A-32D, dynamic to static converter circuits 34A-34C, static logic circuitry 36, and a static storage device 38. It is noted that, while the symbols shown on FIG. 2 for the dynamic logic circuits 30A-30D and 32A-32D resemble AND gates or NAND gates, the symbols are intended, in this context, to represent any dynamic logic circuits performing any logic function. Each dynamic logic circuit 30A-30D and 32A-32D may receive one or more inputs and generate one or more outputs in response to the inputs. Each of the dynamic logic circuits 30A-30D is coupled to receive an ACLK clock signal and has outputs coupled to inputs as shown in FIG. 2. Additionally, in FIG. 2, the dynamic logic gate 30B has an output coupled to the dynamic to static converter circuit 34C, which is further coupled to provide a corresponding static logic input to the storage device 38, which is also clocked by the ACLK clock signal. The dynamic logic gate 30C has an output coupled to the dynamic to static converter circuit 34B, which is further coupled to provide a corresponding static logic input to the static logic circuitry 36. The dynamic logic gate 30D has an output coupled to the dynamic to static converter circuit 34A, which is coupled to provide a corresponding static logic input to the dynamic logic circuit 32A. Each of the dynamic logic circuits 32A-32D is coupled to receive a BCLK clock signal and has outputs coupled to inputs as shown in FIG. 2. Each of the dynamic to static converter circuits 34A-34C is coupled to receive the ACLK clock signal in FIG. 2.

#Generally, the A-phase dynamic logic circuits 30A-30D precharge during the precharge phase of the ACLK clock signal and evaluate during the evaluate phase of the ACLK clock signal. Similarly, the B-phase dynamic logic circuits 32A-32D precharge during the precharge phase of the BCLK clock signal and evaluate during the evaluate phase of the BCLK clock signal. In one embodiment, the precharge phase is the low phase of the corresponding clock signal and the evaluate phase is the high phase of the corresponding clock signal. This example will be used in the remainder of this discussion, although other embodiments may reverse which phases are the precharge and evaluate phases (with corresponding changes to the circuitry).