Output buffer circuit
AssigneeNEC Electronics Corporation
InventorTadashi Fukui
Life of this patent
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Abstract
An output buffer circuit includes a delay circuit for delaying data signal or an inverted version of the data signal by a preset time, a buffer for buffering the data signal with an output impedance of a high value to output the resulting buffered signal, and a three-state buffer, which is controlled responsive to the output of the delay circuit and to the data signal, so that the three-state buffer is activated within the preset time to buffer the data signal and to output the buffered data signal, and is de-activated and turned off outside the preset time.
Claims24
An output buffer circuit applying pre-emphasis distortion to a logic amplitude of a data signal for a preset time when the data signal undergoes a transition to generate a transmission signal of a multi-level waveform and outputting the generated transmission signal to a transmission line, said output buffer circuit comprising:
- means for switching an output impedance to either a power supply or a ground depending on the level of the data signal;
- and
- means for switching the output impedance to a low value and to a high value depending on the time being within and outside the preset time respectively.
Dependencies are inferred from the claim text.