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AssigneeAdvanced Semiconductor Engineering, Inc.
InventorsPo Jen Cheng, Chiu Wen Lee, Jin Zhu Lee, Heng Yu Kung
Estimating the term…
A test assembly for an integrated circuit package includes a package substrate and a test board. The package substrate is provided with a plurality of first contact pads linked in a first daisy chain pattern. The test board has a plurality of second contact pads linked in a second daisy chain pattern and a plurality of test pads. All of the second contact pads are divided into a plurality of groups each connected to one pair of test pads. All of the second contact pads in any group are arranged in a line. The present invention further provides a method of testing an integrated circuit package utilizing the aforementioned package substrate and test board.
A test assembly for an integrated circuit package, the test assembly comprising:
A method of testing an integrated circuit package having a substrate with a plurality of first contact pads linked in a first daisy chain pattern, the method comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Backward citations are indexed for grants only.
Housings; Supporting members; Arrangements of terminals: test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
Contactless testing: using electron beams
Measuring electric variables
Term end not estimated
1. Field of the Invention
The present invention generally relates to a semiconductor device test board and a method for testing an integrated circuit (IC) package, and more particularly to a test board and a testing method for an integrated circuit package having solder bumps.
2. Description of the Related Art
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
FIG. 1 is a top plan view of a conventional semiconductor device test board;
FIG. 2 is a top plan view of a package substrate according to one embodiment of the present invention;
In the IC package testing method according to the present invention, the IC package (not shown) has a package substrate 200 (see FIG. 2) specially designed for solder joint reliability test. The package substrate 200 is of the same size and shape as the substrates for mass production. The package substrate 200 is provided with a plurality of first contact pads 210 linked in a first daisy chain pattern. The package substrate 200 is a ball grid array (BGA) substrate.
The test board 300 according to one embodiment of the present invention, shown in FIG. 3, includes a plurality of second contact pads 310 as denoted with A1 to U21 in FIG. 3 and a plurality of test pads such as test pads N to N5 in FIG. 3. All of the contact pads 310 are linked in a second daisy chain pattern and divided into a plurality of groups each connected to one pair of test pads wherein all of the second contact pads 310 in any group are arranged in a line. For example, the contact pads A1 to U1 are belonged to the same group connected to the test pads N and W5. As described below, the contact pads 310 are designed to be connected to the solder bumps provided on an IC package to be tested.
Now a testing method according to one embodiment of the present invention will be described, which is performed on an IC package with the above mentioned substrate 200 using the test board 300 of the above structure.