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US 2003/0193342 A1Published application
Wafer-level contactor
AssigneeTeradyne, Inc.
InventorsSimon Longson, Alex Slocum
Life of this patent
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AssigneeTeradyne, Inc.
InventorsSimon Longson, Alex Slocum
Estimating the term…
A contact housing adapted for carrying a plurality of compliant contacts is described. The contact housing is for use in contacting a semiconductor wafer-level package having an array of contacts disposed in a predetermined pattern. The contact housing includes a first guide plate formed from a material having a temperature coefficient of expansion approximating that of the semiconductor wafer-level package. The guide plate has a first pattern of apertures formed by a microelectromechanical process such that the pattern of apertures matches the predetermined pattern of contacts on the wafer-level package. A second guide plate is formed similar to the first guide plate, and includes a second pattern of apertures disposed in vertical registration with the first pattern of apertures. A spacer is interposed between the first and second guide plates. The first and second guide plates cooperate with the spacer to form respective receptacles adapted for carrying the plurality of compliant contacts.
A contact housing adapted for receiving a plurality of compliant contacts, the contact housing for use to engage a wafer-under-test, the wafer-under-test having a wafer coefficient of thermal expansion and including an array of conductive contact pads disposed in a wafer-level-packaged pattern, the contact housing including:
A contact housing adapted for receiving a plurality of compliant contacts, the contact housing for use to engage a wafer-under-test, the wafer-under-test having a wafer coefficient of thermal expansion and including an array of conductive contact pads disposed in a wafer-level-packaged pattern, the contact housing including:
A contact housing adapted for receiving a plurality of compliant contacts, the contacts having contact bodies and contact tips, the contact housing for use to engage a wafer-under-test, the wafer-under-test having a wafer coefficient of thermal expansion and including an array of conductive contact pads disposed in a wafer-level-packaged pattern, the contact housing including:
A contact housing adapted for receiving a plurality of compliant contacts, the contacts having contact bodies and contact tips, the contact housing for use to engage a wafer-under-test, the wafer-under-test having a wafer coefficient of thermal expansion and including an array of conductive contact pads disposed in a wafer-level-packaged pattern, the contact housing including:
A wafer-level-contactor, the wafer-level-contactor for use to engage a wafer-under-test, the wafer-under-test having a wafer coefficient of thermal expansion and including an array of conductive contact pads disposed in a wafer-level-packaged pattern, the wafer-level-contactor including:
Dependencies are inferred from the claim text.
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With individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or…:…
External aspects, e.g. related to chambers, contacting devices or handlers: contacting devices, e.g. sockets, burn-in boards or mounting fixtures
Measuring electric variables
Term end not estimated
The invention relates generally to automatic test equipment, and more particularly to a wafer-level contactor used during the process of testing semiconductor devices during high-performance test or burn-in test procedures.
Testing is an important process in the manufacture of semiconductor devices. At both the wafer and packaged-device levels, testing confirms whether individual devices are good or bad before the devices are employed in an electronic assembly.
Generally, a conventional manufacturing test flow for semiconductor devices begins with a probe test at the wafer-level under expected device operating conditions. Data from the test is used for a repair process, if the device is a memory device with redundant rows and columns. Following repair, the devices are diced from the wafer and packaged in a device housing. A burn-in test is then employed, where the devices are exposed to varying temperatures and operating conditions. Lastly, following burn-in, a high-performance test is undertaken on the packaged parts.
The invention will be better understood by reference to the following more detailed description and accompanying drawings in which
FIG. 1 is a partial cross-sectional view of a wafer-level packaging scheme;
FIG. 2 is a high-level block diagram of a wafer-level contactor for engaging the wafer-level packaging of FIG. 1;
Wafer-level burn-in offers significant cost savings for semiconductor manufacturers in terms of increased yields and lower test expenses. By taking advantage of wafer-level-packaging (WLP) techniques, costs can be further reduced by implementing a low-cost wafer-level-contactor in accordance with the present invention.
With reference to FIG. 1, one WLP technique employs a “redistribution layer” 12 that electrically couples a device conductive bond pad 14 with an under-bump metalization layer 16. A solder ball 18 may then be deposited on the metalization layer. The reason for implementing the redistribution layer is to space adjacent contacts further apart in an effort to approximate existing chip-scale-packaging (CSP) and/or ball-grid-array (BGA) contact array pitches. The inventor has discovered that such WLP techniques provide an opportunity to significantly reduce the costs of a wafer-level contactor due to the increased contact-to-contact pitch spacings.
Referring now to FIG. 2, a wafer-level contactor according to one form of the present invention, generally designated 20, includes a contact housing 22 and an array of compliant contacts 24 adapted for receipt within the housing. By employing proven inexpensive replaceable contacts and manufacturing the contact housing according to a microelectromechanicalmachining (MEM) process, significant cost savings are realized.