Circuit for monitoring an open collector output circuit with a significant offset
AssigneeDaimlerChrysler AG
InventorsTimothy P. Philippart, Mikhail Zarkhin
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AssigneeDaimlerChrysler AG
InventorsTimothy P. Philippart, Mikhail Zarkhin
Estimating the term…
A monitoring circuit interfacing an open collector output circuit with a voltage offset, wherein the voltage offset exhibited between the monitoring circuit and the open collector output circuit prevents direct interfacing with a digital input of an adjacent digital circuit. The monitoring circuit of the present invention includes, a first bipolar junction transistor (BJT) connected to an open collector output circuit having a first ground. The first bipolar junction has a second ground that is different from the first ground. The first and second ground creates an appreciable voltage offset therebetween when the first BJT interfaces with the open collector output circuit. The monitoring circuit also includes a second BJT connected to the first BJT in a loop configuration so that at least one of the first and second BJTs increases base current drive to its respective BJT. The monitoring circuit of the present invention therefore maximizes a turn-on rate of its adjacent digital circuit.
A monitoring circuit for interfacing an open collector output stage of an open collector circuit having a first ground with a voltage offset, said voltage offset preventing direct interfacing with a digital input of an adjacent digital circuit, said monitoring circuit comprising:
A monitoring circuit interfacing an open collector output stage with a voltage offset, said voltage offset preventing direct interfacing with a digital input, said circuit comprising:
A monitoring circuit interfacing an open collector output stage with a voltage offset, said voltage offset preventing direct interfacing with a digital input, said circuit comprising:
Dependencies are inferred from the claim text.
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Low-frequency amplifiers, e.g. audio preamplifiers: with semiconductor devices only
Amplifiers
Term end not estimated
The present invention relates generally to a monitoring circuit for a vehicle module. More particularly, the invention relates to a monitoring circuit for a vehicle module interfacing with an open collector circuit residing within a different module than the module containing the monitoring circuit, wherein there is a significant ground voltage offset between the monitoring circuit and the open collector circuit.
A large digital signal system typically includes a plurality of modules which communicate with other modules by transmitting data over a shared signal line. In general, most of these modules interface with at least two other modules which may or may not be under the same limitations and constraints. For example, two different modules residing within a given digital system may be connected to different power supplies and different ground potentials. Such differences in limitations and constraints of two or more different modules may introduce miscommunication between various digital signal modules and may cause erroneous results in a digital signal system. One system which may experience such a difference is a transmitting module having an open collector output circuit and a receiving module having a monitoring circuit. The monitoring circuit of the receiving module interfaces with the open collector output circuit of the transmitting module, and receives an input signal therefrom. These two circuits are described below in greater detail.
FIG. 1 illustrates a typical open collector output circuit 10 contained within a transmitting module of a vehicle. The open collector output circuit 10 includes an input resistor (Rb) 12, a first bipolar junction transistor (BJT) 14, a second BJT 16 and a current limiting resistor (Re) 18. Each of the first and second BJTs 14 and 16, respectively, includes a base junction 28 or 34, an emitter junction 30 or 36, and a collector junction 26 or 32. The base junction 28 of the first BJT 14 is connected to the input resistor (Rb) 12, which transmits an input signal received via the input port 22 from its adjacent circuit. The collector junction 26 of the first BJT 14 provides an output of the open collector output circuit 10 to its adjacent circuit, or a monitoring circuit 50 (FIG. 2) in the present invention. The emitter junction 30 of the first BJT 14 is connected to ground 24 through the current limiting resistor (Re) 18.
Additional objects, advantages, and features of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic diagram of an open collector output circuit, in accordance with the present invention;
FIG. 2 is a schematic diagram of a conventional monitoring circuit; and
With reference to FIG. 3, a monitoring circuit 100, according to the principles of the present invention, will now be described. The monitoring circuit 100 interfaces with an open collector output circuit 10 shown in FIG. 1 via a first signal line 114 that transmits an output signal from the open collector output circuit 10. The first signal line 114 is connected in parallel to a first capacitor (C3) 104 which is connected to an RF ground 106 on the other end. The first signal line 114 is also connected in series to an isolation diode 108. The isolation diode 108 provides isolation to the open collector output circuit 10 so that if the monitoring circuit 100 has a fault, the open collector output circuit 10 will not become non-functional. The isolation diode 108 is connected to a first resistor (R1) 110, in series on the other end, which provides base drive for a first BJT 120. In accordance with the present invention, an NPN BJT is used for the first BJT 120. However, as would be apparent to one skilled in the art, any equivalents thereof may also be used as the first BJT 120. The first resistor 110 is connected in parallel at node A to a second resistor (R2) 112 and a second capacitor (C4) 116. The second resistor (R2) 112 is connected to VDD and the second capacitor (C4) 116, is connected to ground 118. The present invention preferably uses a VDD of five volts with respect to ground 118.
As mentioned briefly above, the first resistor 110 is connected to the first BJT 120 which includes a base junction 146, an emitter junction 148 and a collector junction 144. The emitter junction 148 of the first BJT 120 is connected to node A, and receives emitter current from the open collector output circuit 10 through the first signal line 114. The base junction 146 and the collector junction 144, respectively, of the first BJT 120 are connected to a second BJT 126 in a loop configuration. In accordance with the present invention, a PNP BJT is used as the second BJT 126. However, one skilled in the art will readily recognize that any equivalents thereof can also be used so long as they are compatible with the first BJT 120.
The second BJT 126 also includes a base junction 140, an emitter junction 138, and a collector junction 142. More specifically, the base junction 146 of the first BJT 120 is connected to the collector junction 142 of the second BJT 126 via a third resistor (R3) 130. An optional capacitor (C5) 132 is connected in parallel to the third resistor (R3) 130 to increase the speed of the monitoring circuit 100. At node B, a sixth resistor (R6) 134 is also connected in parallel to the base junction 146 of the first BJT 120 and the third resistor 130. The other end of the sixth resistor 134 is connected to the power supply, VDD. Furthermore, the collector junction 144 of the first BJT 120 is connected to the base junction 140 of the second BJT 126 via a fourth resistor (R4) 122. At node C, a fifth resistor (R5) 124 is connected in parallel to the base junction 140 of the second BJT 126 and the fourth resistor (R4) 122. Likewise, the other end of the fifth resistor 124 is connected to the power supply, VDD. The collector junction 142 of the second BJT 126 is also connected to a seventh resistor (R7) 128, which is connected to the ECU ground 118 on the other end.