System for difference calculation using a quad slope converter

#Slope or integrating type analog to digital converters (ADCs) have typically been used for high precision averaging type measurements. Integrating ADCs are relatively slow devices having low input bandwidths but combine high resolution and low power consumption while advantageously utilizing the available speed. Additionally, ADCs are able to reject high-frequency noise and fixed low frequencies, which makes them useful in noisy industrial environments and applications where high update rates are not required, such as digitizing the outputs of strain gauges and thermocouplers.

#An example of a conventional integrating ADC 100 is shown in FIG. 1. The integrating ADC 100 has two main sections which include an integrating portion 105 for acquiring and integrating an input voltage to produce an integrated voltage signal, and a counter 140 for translating the integrated voltage signal into a digital output value. The integrating portion 105 includes a first switch S1 for switching between an input voltage Vin and a reference voltage Vref. The first switch S1 is connected to an analog amplifier 110 through a resistor R. The output of the analog amplifier 110 is connected to a comparator 120. A capacitor C and a second switch S2 are connected in parallel across the analog amplifier 110. The output of the comparator 120 and a clock signal CLK are input to control logic 130. Responsive to these inputs, control signals from the control logic 130 control the first and second switches S1 and S2 for integrating the input voltage Vin during a fixed integrating time interval (Tcharge) and then de-integrating the reference voltage Vref until the output substantially reaches zero for a time interval (Tdischarge) as shown in FIG. 2.

#In the integrating portion 105, the analog amplifier 110 charges the capacitor C with the input voltage Vin (first switch S1 is set to Vin). In the de-integrating portion, the analog amplifier 110 discharges the capacitor C with an opposite-polarity reference voltage Vref (first switch S1 is set to Vref). Vin is integrated for the fixed time interval Tcharge that corresponds to the maximum count of the counter 140. At the end of the fixed time interval Tcharge, the counter 140 is reset and Vref is applied to the input of the analog amplifier 110. The analog amplifier 110 then de-integrates until an output of zero is reached, which defines the end of the time interval Tdischarge, at which point in time the counter 140 is stopped and the analog amplifier 110 is reset (second switch S2 is momentarily closed).

#The invention will be more fully understood by reference to the following detailed description of the invention in conjunction with the drawings, of which:

#FIG. 1 illustrates a conventional integrating ADC;

#FIG. 2 illustrates a voltage waveform associated with the conventional integrating ADC;

#The embodiments of the present invention are directed to a system and method for measuring signals in a non-linear network. FIG. 3 illustrates a system according to an embodiment of the present invention which includes an integrating ADC circuit 310 for integrating and de-integrating input voltages, a counter 320 operatively communicative with the integrating ADC circuit 310 for outputting a digital output value of the integrated voltage, an ADC controller 330 operatively communicative with the integrating ADC circuit 310 and the counter 320 for performing control and measurement operations, and a load 340 connected to the ADC controller 330.

#In particular, the ADC controller 330 performs dual slope measurement cycles in which first and second excitation voltages are sequentially inputted to the integrating ADC circuit 310 during dual slope measurement cycles. Within one dual slope measurement cycle, at least four measurement phase cycles are included. In a first phase, a first excitation voltage is input from the ADC controller 330 to the integrating ADC circuit 310 for generating a first integrated voltage after integrating the first excitation voltage for a fixed time interval. During the second phase of the measurement cycle, the integrating ADC circuit 310 de-integrates the first integrated voltage until a predetermined threshold voltage is reached and a first digital output value is generated. After the threshold voltage is reached, the counter 320 obtains a count value corresponding to a first digital output value which is then stored by the ADC controller 330 for use in subsequent phases.

#In the third phase of the measurement cycle a second excitation voltage is input from the ADC controller 330 to the integrating ADC circuit 310 for generating a second integrated voltage after integrating the second excitation voltage for the fixed time interval. During the fourth measurement phase, the ADC controller 330 obtains a second count value corresponding to a second digital output value from the integrating ADC circuit 310 and compares the second count value with the stored first count value. When the ADC controller 330 determines that the second count value is equal to the first count value, the counter 320 is reset to zero. After being reset, the integrating ADC circuit 310 continues to de-integrate the second integrated voltage and the counter 320 resumes counting until the predetermined threshold voltage is reached. Thereby, at the end of this fourth measurement phase, the second count value is obtained with a difference calculation that has been automatically performed thereon.