Wafer-level package with a cavity and fabricating method thereof

#1. Field of the Invention

#The present invention relates to a method for fabricating a semiconductor package at wafer level, and more particularly to a method for fabricating a micro device package with a cavity.

#2. Description of the Related Art

#Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

#FIG. 1 is a cross section view of a conventional chip scale package of prior art.

#FIG. 2 is a schematic cross section view of a micro device package according to a first embodiment of the present invention.

#Referring now to FIG. 2, it depicts a package with a cavity according to a first embodiment of the present invention. The package 50 mainly comprises a base chip 10, a plurality of conductive bumps 14, and a cap chip 20. The base chip 10 has a micro device 16 electrically connected to a plurality of bonding pads 12. The plurality of conductive bumps 14 are formed on the bonding pads 12, respectively. The cap chip 20 has a plurality of conductive vias 20a. The shape, dimension, and amount of the conductive vias 20a depend on the design requirement, such as conductivity thereof, without any limitation. The cap chip 20 is further provided with a plurality of bonding pads (not shown) disposed on the outer surface thereof corresponding to the conductive vias 20a. It will be apparent to those skilled in the art that these bonding pads are electrically connected to the external substrate or printed circuit board (PCB) by bonding wires, solder bumps or the other known conductive structure, whereby the base chip 10 is electrically connected to the external circuit through the conductive bump 14 and the conductive via 20a as well as the bonding wire or the solder bump.

#The package 50 is surround and sealed with a seal member 32 to form a hermetical cavity 30a around the micro device 16. The cap chip 20 can be made of a high resistivity semiconductor material, such as single crystal silicon, fiberglass reinforced bismaleimide triazine (BT) resin or FR-4 fiberglass reinforced epoxy resin. Preferably, both of the base chip 10 and the cap chip 20 are made of the same material, such as silicon wafers, to avoid thermal expansion mismatch, and to be handled in the same processes and conditions with normal silicon wafers during the following manufacturing process.

#The micro device 16 is disposed on the base chip 10 and can be provided with the micro active device, such as the integrated circuit, the micro mechanics, the moving part, or the micro passive device, such as various sensors. The micro device 16 is electrically connected to the bonding pads 12 through the channels or wires (not shown). Since the package 50 has the hermetical cavity 30a, the moving part of the micro device 16 can be substantially moved within the cavity 30a.