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AssigneeNEC Electronics Corporation
InventorsNobuaki Takahashi, Kiminori Ishido, Syuichi Shibazaki, Kenta Ogawa
Estimating the term…
There is disclosed a fabrication method comprising: stacking and forming an Ni bond layer 3 and oxidation preventive layer 4 on a Cu interconnection layer 2 formed on the surface of a BGA package 1 in an electroless plating process; and applying a flux 5 to coat the oxidation preventive layer 4. Moreover, the method comprises: laying a Cu-added solder ball bump 6 onto the oxidation preventive layer 4; and performing a heat treatment in a temperature range of 190° C. to 220° C. to melt/bond the bump into the Ni bond layer 3. Sn and Cu in the Cu-added solder ball bump 6 rapidly react with Ni in the Ni bond layer 3 to form a diffusion inhibitive alloy layer 7. Subsequently, an electrode pad 10 on a mother board 9 which is a interconnection substrate is molten/bonded into the Cu-added solder ball bump 6, and a semiconductor device 8 is mounted on a mother board 9.
A semiconductor device for use in connecting a semiconductor chip, semiconductor package and interconnection substrate to one another, comprising:
A fabrication method for a semiconductor device comprising an electrode structure for use in connecting a semiconductor chip, semiconductor package, and interconnection substrate to one another, the method comprising:
A fabrication method for a semiconductor device comprising an electrode structure for use in connecting a semiconductor chip, semiconductor package, and interconnection substrate to one another, the method comprising:
A fabrication method for a semiconductor device comprising an electrode structure for use in connecting a semiconductor chip, semiconductor package, and interconnection substrate to one another, the method comprising:
A fabrication method for a semiconductor device comprising an electrode structure for use in connecting a semiconductor chip, semiconductor package, and interconnection substrate to one another, the method comprising:
A fabrication method for a semiconductor device comprising an electrode structure for use in connecting a semiconductor chip, semiconductor package, and interconnection substrate to one another, the method comprising:
A fabrication method for a semiconductor device comprising an electrode structure for use in connecting a semiconductor chip, semiconductor package, and interconnection substrate to one another, the method comprising:
Dependencies are inferred from the claim text.
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Reinforcing of the conductive pattern: finish plating of conductors, especially of copper conductors, e.g. for pads or lands
By soldering: solder materials or compositions specially adapted therefor
Surface contacts, e.g. bumps: using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
Metal processing: punching metal foil, e.g. solder foil
Term end not estimated
1. Field of the Invention
The present invention relates to a semiconductor device and method for fabricating the device, particularly to a semiconductor device which includes an electrode structure bonded through a solder and method for fabricating the device.
2. Description of the Prior Art
FIG. 1A depicts a schematic sectional view in order of steps of solder ball bump formation and semiconductor device mounting according to a prior art;
FIG. 1B depicts a schematic sectional view following FIG. 1A in order of the steps of the solder ball bump formation and semiconductor device mounting;
FIG. 1C depicts a schematic sectional view following FIG. 1B in order of the steps of the solder ball bump formation and semiconductor device mounting;
Next, a semiconductor integrated circuit of an embodiment of the present invention will be described in detail with reference to the drawings.
First, a first embodiment of the present invention will be described with reference to FIGS. 2 to 4. FIG. 2 depicts a sectional view of a step order, showing formation of a solder ball bump of a BGA package using Pb—Sn alloy solder (tin-lead solder) of an eutectic composition in the present invention and connection to a mother board which is a interconnection substrate. The present invention is characterized in that a micro amount of Cu atoms are added to the solder ball bump. Moreover, FIGS. 3 and 4 depicts graphs showing an effect generated in this case. Here, a semiconductor chip is mounted on the BGA package.
In the same manner as described in the prior art, as shown in FIG. 2A, Ni bond layers 3 are formed on Cu interconnection layers 2 formed on the surface of a BGA package 1 in an electroless plating process. Here, an electroless plating solution is a chemical obtained by adding reducing agents such as hypophosphorous soda (NaH2PO2) to an aqueous solution of nickel salt. Moreover, the Ni bond layers 3 and oxidation preventive layers 4 are stacked and formed. Thereafter, fluxes 5 are applied to coat the oxidation preventive layers 4.