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AssigneeRenesas Technology Corp.
InventorsMiharu Otani, Jun Tanaka, Katsuhiko Hotta, Yasumichi Suzuki, Takashi Inoue
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A semiconductor device capable of high speed operation with a substantially small interlayer capacitance is produced by steps of using an insulating film comprising an organic insulating film and an insulating film composed of an organometallic polymer material as an interlayer insulating film formed by coating, patterning the insulating film in a semi-thermosetting state, etching the organic insulating film as the lower layer by means of the organometallic polymer as a mask, using a plasma gas containing oxygen as the main component, and then conducting ultimate baking treatment of these insulating films.
A semiconductor device comprises a wiring layer and an interlayer insulating film layer, characterized in that the interlayer insulating film layer comprises a first insulating layer composed of an organic insulating film as a lower layer and a second insulating layer composed of an organometallic polymer laid thereon as an upper layer.
A semiconductor device comprising a wiring layer and an interlayer insulating film layer, characterized in that the interlayer insulating film layer is a second insulating layer composed of an organometallic polymer.
An electronic circuit device comprising a wiring layer and an interlayer insulating film layer, characterized in that the interlayer insulating film layer comprises a first insulating layer composed of an organic insulating film as a lower layer and a second insulating layer composed of an organometallic polymer laid thereon as an upper layer.
A process for producing a semiconductor device, characterized by comprising a step of applying an organic insulating film material to a substrate, thereby forming a first insulating layer, a step of applying an organometallic polymer material to the first insulating layer, thereby forming a second insulating layer, a step of forming an opening-forming resist pattern on the second insulating layer, a step of forming an opening in the second insulating layer by means of the resist pattern as a mask, a step of forming an opening in the first insulating layer by means of the resist pattern and the second insulating layer as a mask by dry etching, while removing the resist, and a step of baking the first insulating layer and the second insulating layer.
A process for producing a semiconductor device, characterized by a step of applying an organic insulating film material to a substrate, thereby forming a first insulating layer, a step of applying an organometallic polymer material to the first insulating layer, thereby forming a second insulating layer, a step of forming an opening-forming resist pattern on the second insulating layer, while forming an opening in the second insulating layer, a step of forming an opening in the first insulating layer by dry etching, while removing the resist, and a step of baking the first insulating layer and the second insulating layer.
A process for forming a semiconductor device, characterized by comprising a step of applying an organic insulating film material to a substrate, thereby forming a first insulating layer, a step of applying an organometallic polymer material to the first insulating layer, thereby forming a second insulating layer, a step of forming an opening in the second insulating layer, a step of forming an opening in the first insulating layer by dry etching by means of the second insulating layer as a mask, and a step of baking the first insulating layer and the second insulating layer.
A semiconductor memory device, comprising a memory device-containing semiconductor substrate, an insulating interlayer laid on the semiconductor substrate, an upper wiring layer and a wiring material, provided with a partition wall surrounding device peripheral region to prevent moisture absorption and permeation through the peripheral region (the protection wall will be hereinafter referred to as guard ring), characterized in that the insulating interlayer comprises an insulating film composed of an organic insulating film as a lower layer and an insulating film composed of a ladder silicone-based polymer material laid thereon as an upper layer, one end of the guard ring provided in the outermost peripheral region of the memory device is connected to the upper wiring layer, while the other end thereof is embedded in the semiconductor substrate.
A semiconductor device comprising a MOS transistor-containing semiconductor substrate, and a BPSG layer, a wiring layer, an insulating interlayer and a protective film, successively formed on the semiconductor substrate, characterized in that an electroconductive plug provided through the BPSG layer and insulating interlayer is connected to the semiconductor substrate through the wiring layer, the insulating interlayer comprises an insulating film composed of an organic insulating film as a lower layer and an insulating film composed of a ladder silicone-based polymer material laid thereon as an upper layer, and the protective film is provided so as to enclose the edges of the BPSG layer and the insulating interlayer.
Dependencies are inferred from the claim text.
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Organic materials, e.g. photoresists: carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC
By exposure to a gas or vapour: by exposure to a plasma
Characterised by the type of materials: laminate layers, e.g. stacks of alternating high-k metal oxides
Of organic materials: by chemical means
Term end not estimated
The present invention relates to a semiconductor device with an organic insulating film having a low dielectric constant in an interlayer insulating film and a process for producing the same.
With increasing integration density of semiconductor devices and chip size reduction, formation of finer wirings or a narrower pitch in a multilayer structure is now in progress. Consequently, the time of delay in propagation of signals through wirings, i.e. delay in signal propagation through wirings, becomes longer, causing a serious problem in the use of semiconductor device-mounted electronic appliances.
Generally, the speed of signal propagation through wirings depends on a product (RC) of wiring resistance (R) by interwiring capacitance (C), and thus it is necessary for improving the delay in signal propagation through wirings to lower the wiring resistance and decrease the interwiring capacitance, i.e. to make the dielectric constant of an interlayer insulating film lower.
FIG. 1 shows process steps for producing the conventional semiconductor device.
FIG. 2 shows process steps for producing a semiconductor device according to Example 1.
FIG. 3 shows process steps for producing a semiconductor device according to Example 2.
In FIGS. 1 to 20, reference numerals have the following meanings:
1 . . . substrate, 2 . . . organic low dielectric constant film, 3 . . . silicon oxide film, 4 . . . resist pattern, 5 . . . opening, 201, 301, 401, 701, 801, 901 . . . substrate, 501, 601 . . . lower wiring layer, 202, 302, 402, 502, 702, 802, 903, 1101, 1213, 1313, 1408, 1508, 1606, 1808 . . . first insulating layer, 203, 303, 403, 503, 602, 703, 803, 904, 1216, 1316, 1409, 1509, 1607, 1809 . . . second insulating layer, 504, 603 . . . tungsten wiring, 704 . . . via hole, 705, 804, 1220, 1320 . . . third insulating layer, 706, 1221, 1321 . . . fourth insulating layer, 807, 1407, 1411, 1414, 1507, 1511, 1514 . . . wiring, 1223, 1323 . . . upper wiring, 1201, 1301 . . . p-type semiconductor substrate, 707, 1202, 1302 . . . trench, 1203, 1204, 1303, 1304 . . . oxide film, 1205, 1305 . . . n-type well region, 1206, 1306 . . . p-type well region, 1207, 1307 . . . gate insulating layer, 1208, 1308 . . . gate electrode, 1209, 1309 . . . cap insulating layer, 1210, 1212, 1310, 1312 . . . n-type semiconductor region, 1211, 1311 . . . side-wall spacer, 1214A, 1214B, 1217, 1314A, 1314B, 1317 . . . connecting hole, 906, 909, 1215, 1218, 1315, 1318, 1406, 1410, 1413, 1506, 1510, 1513 . . . electroconductive plug, 1219, 1224, 1319, 1324, 1416, 1516 . . . silicon nitride film, 1222 . . . tungsten, 1322 . . . guard ring portion, 1225, 1325, 1417, 1517 . . . polyimide film, 901, 1401, 1501, 1601, 1701 . . . semiconductor substrate, 1402, 1502 . . . element isolation region, 1403, 1503 . . . MOS transistor, 1404, 1504 . . . insulating film, 1405, 1505 . . . BPSG film, 21, 51, 71, 72, 81, 91, 92, 93, 94, 101, 102, 103, 110, 111, 1412, 1415, 1512, 1515, 1811, 1813 . . . laminated interlaminar insulating film, 1416, 1602, 1702 . . . passivation film, 1603, 1703 . . . aluminum pad, 1604, 1704, 1902, 2002 . . . polyimide chip coat film, 1605, 1705 . . . rearrangement wiring, 1606, 1706 . . . insulating layer, 1608, 1707 . . . under-bump metal layer, 1609, 1708 . . . solder bump, 1801, 1806 . . . ceramic layer, 1802 . . . inner layer wiring, 1803 . . . upper electrode (Ni layer), 1804 . . . lower electrode (Ni layer), 1805 . . . Au layer, 1807 . . . first aluminum wiring layer, 1810 . . . second aluminum wiring layer, 1812 . . . third aluminum wiring layer, 1814 . . . Cr/Ni—Cu layer, 1815 . . . Ni/Au layer, 204, 304, 805, 806, 905, 1103 . . . resist pattern, 902 . . . first wiring layer, 907 . . . second wiring layer, 910 . . . third wiring layer, 912 . . . fourth wiring layer, 1003, 1005 . . . copper, 914, 1007, 1104 . . . fifth wiring layer, 1001, 1101 . . . organic insulating layer, 1002, 1102 . . . polymer insulating layer, 1901, 2001 . . . semiconductor element, 1903, 2005, 2006 . . . outer terminal, 1904 . . . polyimide film, 1905, 2004 . . . gold wire, 1906, 2003 . . . epoxy resin.
The present semiconductor device is provided with an interlayer insulating film layer laid on a wiring layer, which comprises at least one of layers each comprising a first insulating layer composed of an organic insulating film as a lower layer and a second insulating layer composed of an organometallic polymer material laid thereon as an upper layer.