Bipolar transistor and method of fabricating the same
AssigneeNEC Electronics Corporation
InventorHiroki Fujii
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AssigneeNEC Electronics Corporation
InventorHiroki Fujii
Estimating the term…
A device isolation region surrounds first and second device regions of a semiconductor substrate and a patterned deep-trench isolation region is embedded through the device isolation region into the substrate. First and second bipolar transistors are respectively formed in the device regions. Each transistor has a collector region and a base region in the substrate, and an emitter embedded in an insulation layer above the base region. Space savings, low collector resistance and low collector-substrate capacitance are achieved by embedding a collector trench contact into boundary portions of the deep-trench and device isolation regions deeper into the substrate to establish an electrical contact with the corrector region. With a single photoetching process, the insulation layer is etched to create openings for the collector trenches simultaneously with openings for the emitters and base regions. Similar structure of the collector trench contact is used advantageously for double-polysilicon self-aligned bipolar transistors.
A bipolar transistor comprising:
A semiconductor device comprising:
A semiconductor device comprising:
A method of fabricating a bipolar transistor, comprising:
Dependencies are inferred from the claim text.
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Manufacture or treatment: of vertical BJTs
Manufacture or treatment: integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
Characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs: combinations of…
Term end not estimated
1. Field of the Invention
The present invention relates generally to semiconductor devices, and more specifically to bipolar transistors and a method of fabricating high-frequency bipolar transistors,
2. Description of the Related Art
The present invention will be described in detail further with reference to the following drawings, in which:
FIG. 1 is a top plan view of a pair of bipolar transistors constructed according to a first embodiment of the present invention;
FIG. 2 is a vertical cross-sectional view taken along the line 2-2 of FIG. 1;
Referring now to FIGS. 1 and 2, there is shown an integrated circuit of bipolar transistors according to a first embodiment of the present invention is illustrated. A pair of bipolar transistors is integrated on a p-type silicon substrate 1. One photoetching process is used to form a deep-trench isolation region 3. Deep trench 3 extends vertically through a device isolation region 2 to a point near the bottom of the substrate and encloses the bipolar transistors and isolates them from each other. The center portion of isolation trench 3 serves not only as an isolation wall between the devices but also as a space for accommodating their collector contacts 16a, 16b. This structure eliminates the need to form a diffusion layer which would have been required for the prior art collector trench, while allowing collector contacts to directly contact a region 300 to 600 nanometers deep from the surface of the substrate 1 where the phosphorus concentration of the n-type well is highest. As a result, the space occupied by the bipolar transistors is reduced and hence their collector resistance Rc and collector-substrate capacitance Csub are decreased using only one photoetching process.
The integrated circuit of the bipolar transistors is fabricated in a manner as will be described below with reference to FIGS. 3A to 3G.
In FIG. 3A, a device isolation oxide layer 2 is formed on the surface of the substrate 1 and a deep trench 3 is etched through the device isolation region 2 to a depth of 300 to 600 nanometers near the bottom of the substrate. Deep trench 3 encloses areas where impurities will be diffused,