Interlocking conductor method for bonding wafers to produce stacked integrated circuits

#The present invention relates to integrated circuits, and more particularly, to a method for bonding wafers together to form integrated circuits having a stack of thin layers.

#Modem integrated circuits are typically constructed in a thin layer in a semiconducting layer on a substrate wafer such as silicon. This essentially two-dimensional structure limits both the size of the integrated circuit and the speed at which the circuit operates. The speed at which an integrated circuit operates is determined by the distance between the farthest separated components that must communicate with one another on the chip. For any given number of components, the path lengths will, in general, be significantly reduced if the circuit can be laid out as a three dimensional structure consisting of a number of vertically-stacked layers of circuitry, provided the vertical distances between the layers are much smaller than the width of the chips that make up the individual layers.

#One promising scheme for providing such stacked structures utilizes a method for stacking and bonding entire wafers. In this method, integrated circuits are fabricated on conventional wafers. Two wafers are bonded vertically by thinning one wafer in a first coarse thinning operation by removing material from the back of the wafer. The circuitry on the front surface of each wafer is covered with an insulating layer having metal filled vias that make contact with the underlying circuitry and act as electrical connection points between the two wafers. In addition, the front surfaces of the wafers include bonding pads that are planar metal areas that do not connect to the underlying circuitry. The bonding pads are provided to increase the bonded area. The front surfaces of the wafers are then placed in contact with one another so that the bonding pads on one wafer are in contact with the pads on the other wafer. Thermal diffusion bonding is then used to bond the metal pads, and hence, the wafers together. One of the wafers is then further thinned to a thickness of a few microns by etching or mechanically grinding the back surface of that wafer further. Once the wafer has been thinned, a new set of vias is opened in the backside and filled with metal to provide the connection points to the pads on the front side of the wafer that make connections with the circuitry in the wafer. In addition, a new set of bonding pads is formed on the backside of the wafer so that another wafer can be bonded to the stack. The process is then repeated until the desired number of layers has been bonded to form the three-dimensional stack. The three-dimensional stack is then cut into three-dimensional chips and packaged.

#FIG. 1 is a cross-sectional view of a portion of a stacked integrated circuit 10 according to the present invention.

#FIG. 2 is a cross-sectional view of a wafer 100 used as a starting point for a component layer.

#FIG. 3 is a cross-sectional view of wafer 100 after a via 120 has been etched through the dielectric layers and into substrate 110.

#The manner in which the present invention provides its advantages may be more easily understood with reference to FIG. 1 which is a cross-sectional view of a portion of a stacked integrated circuit 10 according to the present invention having a base component layer 20 and two stacked component layers shown at 30 and 40. Each component layer includes an integrated circuit layer that is constructed on a substrate using conventional integrated circuit fabrication techniques. To simplify the following discussion, it will be assumed that the integrated circuit layer is constructed on a conventional silicon substrate in the form of a wafer. The integrated circuit layers corresponding to component layers 20, 30, and 40 are shown at 22, 32, and 42, respectively. The substrates on which these layers were constructed are shown at 21, 31, and 41, respectively. The integrated circuit layer is covered with one or more layers of dielectric such as SiO2 in which various metal conductors are constructed and connected to the circuitry by vias. To simplify the drawing, only the metal conductors that are to be connected to components on other component layers are shown in the drawing. Exemplary conductors of this type are shown at 25, 35, and 45 together with the dielectric layers that are shown at 23, 33, and 43.

#Connections between the various component layers are provided by vertical conductors that pass through one or more component layers. A typical vertical conductor is shown at 50. Vertical conductor 50 is constructed from component conductors shown at 51-53 by thermal diffusion bonding of the component conductors. The thermal diffusion bonding of the component conductors also bonds the various component layers together.

#It should be noted that, in general, there are thousands, if not tens of thousands, of vertical conductors in a typical stacked integrated circuit. Hence, the diameters of the vias are preferably as small as possible. The minimum diameter of a via is determined by the aspect ratio permitted by the metallization process used to fill the via. Vias with aspect ratios of greater than 5 are difficult to fill reliability. Hence, it is advantageous to have the component layers be as thin as possible. In addition, thin component layers are more flexible. The flexibility improves the strength of the stacked structure and reduces cracking or other damage caused by thermal stress.