High voltage lateral DMOS transistor having low on-resistance and high breakdown voltage

#This application claims priority of Korean patent application Serial No. 01-20168, filed Apr. 16, 2001.

#1. Field of the Invention

#The present invention relates to a power semiconductor device, and more particularly, to a high voltage lateral Double diffused Metal Oxide Semiconductor (DMOS) transistor having low on-resistance and high breakdown voltage.

#The above objective and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:

#FIG. 1 is a layout diagram of an example of a conventional high voltage lateral Double diffused Metal Oxide Semiconductor (DMOS) transistor employing a double Reduced Surface Field (RESURF) structure;

#FIG. 2 is a cross-section of the high voltage lateral DMOS transistor of FIG. 1, taken along the line 11-11′;

#Hereinafter, an embodiment of the present invention will be described in detail with reference to the attached drawings. The present invention is not restricted to the following embodiment, and many variations are possible within the sprit and scope of the present invention. The embodiment of the present invention is provided in order to more completely explain the present invention to anyone skilled in the art. For example, n-type regions may be p-type regions, and vice versa. In the drawings, the thicknesses of layers or regions are exaggerated for clarity and the same reference numerals denote the same members.

#Referring to FIGS. 3 through 5, a p−well region 110 and an n− well region 120 are formed in the upper portion of a p-type semiconductor substrate 100. The p-well region 110 may be omitted. The n− well region 120 is used as a drift region. A p-body region 130 having a channel region 135 on its surface and a deep p+ body region 140 surrounded by the p-body region 130 are formed in the upper portion of the p− well region 110. An n+ source region 150 and a p+ contact region 160 surrounded by the n+ source region 150 are formed in the upper portion of the pbody region 130 including its surface. The channel region 135 is formed in the upper portion of the p-body region 130, that is, between the n+ source region 150 and the n-well region 120.

#A plurality of p-well regions 170 and an n+ drain region 180 are formed within the n-well region 120. The p-well regions 170 are horizontally spaced out between the channel region 135 within the p-body region 130 and the n+ drain region 180. As seen from a plan view shown in FIG. 3 and a cross-section shown in FIG. 5, each p-well region 170 is shaped like a column. The top surfaces of the p-well regions 170 and the top surface of the n-well region 120 are on the same horizontal plane, and the bottom surfaces of the p-well regions 170 and the bottom surface of the n-well region 120 are on the same horizontal plane. The top and bottom surfaces of each p-well region 170 have a circular shape. It is apparent that each p-well region 170 may be formed to have polygon-shaped top and bottom surfaces. However, the circular shape is most preferable in order to suppress concentration of an electric field on each comer.