Self-aligned multi-bit flash memory cell and its contactless flash memory array

A contactless multi-bit flash memory array, comprising:

• a semiconductor substrate of a first conductivity type having a plurality of parallel shallow-trench-isolation (STI) regions and a plurality of active regions formed alternately over said semiconductor substrate, wherein each of the plurality of parallel STI regions is filled with a raised field-oxide layer;
• a plurality of common-source bus-line regions and a plurality of virtual-gate regions being formed alternately and transversely to the plurality of parallel STI regions, wherein:
• each of the plurality of virtual-gate regions comprises a pair of gate regions being located in each side portion with a common-drain bus-line region being located between the pair of gate regions;
• each of the plurality of common-source bus-line regions comprises a pair of first sidewall dielectric spacers being formed over each sidewall of nearby virtual-gate regions and on a first flat bed being alternately formed by a common-source diffusion region in said active region and an etched first raised field-oxide layer in said parallel STI region, a common-source conductive bus line being formed over said first flat bed between the pair of first sidewall dielectric spacers, and a first planarized thick-oxide layer being formed over said common-source conductive bus line and the pair of first sidewall dielectric spacers;
• each of said common-drain bus-line regions comprises a pair of second sidewall dielectric spacers being formed over each sidewall of the pair of gate regions and on a second flat bed being alternately formed by a common-drain diffusion region in said active region and an etched second raised field-oxide layer in said parallel STI region, a common-drain conductive bus line being formed over said second flat bed between the pair of second sidewall dielectric spacers, and a second planarized thick-oxide layer being formed over said common-drain conductive bus line and the pair of second sidewall dielectric spacers;
• a plurality of self-aligned multi-bit flash memory cells being formed in each of the pair of gate regions for each of the plurality of virtual-gate regions, wherein each of the plurality of self-aligned multi-bit flash memory cells comprises a first floating-gate structure having a first floating-gate layer formed on a first gate-dielectric layer and a second floating-gate structure having a second floating-gate layer formed on a second gate-dielectric layer being formed in said active region, a spacing dielectric layer being formed between said first floating-gate structure and said second floating-gate structure, and a planarized control-gate layer spaced by an intergate dielectric layer being at least formed on said first floating-gate structure, said spacing dielectric layer, and said second floating-gate structure;
• and
• a plurality of word lines being formed transversely to the plurality of common-source/drain conductive bus lines, wherein each of the plurality of word lines comprises a first interconnect-metal layer and a plurality of planarized control-gate layers in each row being patterned and etched by a hard masking layer having a third masking dielectric layer aligned above each of the plurality of active regions and two sidewall dielectric spacers being formed over each sidewall of said third masking dielectric layer.

A contactless multi-bit flash memory array, comprising:

• a plurality of common-source conductive bit lines being formed in parallel in a first direction;
• a plurality of paired multi-bit flash memory cells being formed between the plurality of common-source conductive bit lines, wherein a plurality of common-source diffusion regions of the plurality of paired multi-bit flash memory cells are electrically connected to the plurality of common-source conductive bit lines;
• a plurality of common-drain conductive bit lines being formed between the plurality of paired multi-bit flash memory cells, wherein a plurality of common-drain diffusion regions of the plurality of paired multi-bit flash memory cells are electrically connected to the plurality of common-drain conductive bit lines;
• and
• a plurality of word lines integrated with a plurality of control-gates of the plurality of paired multi-bit flash memory cells being simultaneously patterned and formed in a second direction being perpendicular to said first direction, wherein each gate region of the plurality of paired multi-bit flash memory cells comprises a first floating-gate structure having a first floating-gate layer formed on a first gate-dielectric layer and a second floating-gate structure having a second floating-gate layer formed on a second gate-dielectric layer;
• a spacing dielectric layer being formed between said first floating-gate structure and said second floating-gate structure;
• an intergate-dielectric layer being at least formed over said first floating-gate structure, said second floating-gate structure and said spacing dielectric layer;
• and a planarized conductive layer acted as said control-gate being at least formed on said intergate dielectric layer.