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AssigneeIHP GmbH-Innovations for High Performance Electronics
InventorHans-Joerg Osten
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The invention concerns an electronic component with a first layer (16) of metallically conductive material, a second layer (12) of semiconductor material and a third layer (14) between the first (16) and second (12) layers, wherein the third layer (14) includes a dielectric and is adapted to inhibit or prevent charge carrier transport both from the first to the second layer and also from the second to the first layer. According to the invention the dielectric contains praseodymium oxide in predominantly single crystal phase. 1 Berlin 25 Jul. 2001 Our ref: IB1063 JVO/bfr Applicants/proprietors: IHP GmbH-Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Office ref: New application
An electronic component with a first layer (16) of metallically conductive material, a second layer (12) of semiconductor material and a third layer (14) between the first (16) and second (12) layers, wherein the third layer (14) includes a dielectric and is adapted to inhibit or prevent charge carrier transport both from the first to the second layer and also from the second to the first layer, characterised in that the dielectric contains praseodymium oxide in predominantly single crystal phase.
An electronic component as set forth in one of the preceding claims characterised in that the third layer has an amorphous region (14.1).
An electronic component as set forth in one of the preceding claims characterised in that the extent of the amorphous region (14.1) in the direction of the sequence of layers is at a maximum 20% of the total extent of the third layer (14) in said direction.
An electronic component as set forth in one of the preceding claims characterised in that the extent of the third layer (14) in the direction of the sequence of layers is at a maximum 50 nanometers.
An electronic component as set forth in one of the preceding claims characterised in that the dielectric comprises praseodymium oxide.
An electronic component as set forth in one of the preceding claims characterised in that the dielectric constant of the dielectric is between 20 and 40.
An electronic component as set forth in one of the preceding claims characterised in that the dielectric contains praseodymium oxide Pr2O3.
An electronic component as set forth in one of the preceding claims characterised in that the dielectric contains Pr2O3 in a D53-crystal structure or D52-crystal structure.
An electronic component as set forth in one of the preceding claims characterised in that the component is in the form of a field effect transistor (10).
An electronic component as set forth in one of the preceding claims characterised in that the component is in the form of a scaled CMOS-FET, wherein the first layer is in the form of a gate electrode (16) and the third layer (14) adjoins a channel (22) provided in the second layer (12) in a direction perpendicular to the sequence of layers between a source structure (18) and a drain structure (22).
An electronic component as set forth in one of the preceding claims characterised in that at its interface to the third layer (14) the second layer (12) comprises silicon with a (001)- or with a (111)-crystal orientation.
A process for the production of an electronic component comprising a step of depositing a praseodymium oxide-bearing material layer from a gaseous atmosphere on a substrate characterised in that the praseodymium oxide-bearing material layer is deposited at a substrate temperature of between 500° C. and 800° C.
A process as set forth in one of the preceding claims characterised by a step of thermal curing, which follows the deposit step, wherein the substrate temperature during the thermal curing step is at least 400° C. and at most 1000° C.
A process as set forth in one of the preceding claims characterised in that the temperature of the layer during the thermal curing step is between 550° C. and 700° C.
Dependencies are inferred from the claim text.
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On single crystalline silicon, e.g. chemical oxidation using a liquid: with a treatment, e.g. annealing, after the formation of the insulator and…
On single crystalline silicon, e.g. chemical oxidation using a liquid: by deposition, e.g. evaporation, ALD or laser deposition
Characterised by the insulator, e.g. by the gate insulator: having ferroelectric layers
Characterised by the insulator, e.g. by the gate insulator: comprising metallic compounds, e.g. metal oxides or metal silicates
Term end not estimated
The invention concerns an electronic component with a first layer of metallically conductive material, a second layer of semiconductor material and a third layer between the first and second layers, wherein the third layer includes a dielectric and is adapted to inhibit or prevent charge carrier transport both from the first to the second layer and also from the second to the first layer.
The invention further concerns a process for the production of an electronic component including a step of depositing a praseodymium oxide-bearing material layer on a substrate.
Electronic components of the above-specified kind are usually identified by the abbreviation MIS (metal insulator semiconductor) or, in their most common and most significant configuration, MOS (metal oxide semiconductor). There are known for example MOS diodes, MOS field effect transistors (MOSFET), scaled MOSFETs in which material parameters such as doping are adapted to reduce lateral dimensions of the component structure, modulation-doped MODFETs or DRAM structures.
Further advantages of the invention are described in the description hereinafter of some embodiments by way of example with reference to the drawing in which:
FIG. 1 shows an X-ray diffraction spectrum of a Pr2O3 layer on Si (001),
FIG. 2 shows the result of a CV measurement on a second Pr2O3 layer grown on p-Si,
FIG. 1 shows an X-ray diffraction spectrum of a 13.4 nanometer thick Pr2O3 layer on (001) silicon. That layer was produced at a substrate temperature of 625° C. by means of molecular beam epitaxy using solid starting material (Pr6O11) and then thermally cured at a substrate temperature of 600° C. for five minutes. The Figure shows the diffracted X-ray intensity in units of counting pulses of a detector as a function of double the diffraction angle (2 theta). The spectrum shows a dominant diffraction line at 2 theta=70° which is to be attributed to diffraction at the silicon lattice. At a double diffraction angle of about 45° there is a second diffraction line with in comparison a somewhat lesser degree of intensity than that of the silicon peak. That line is to be attributed to diffraction of the X-ray light at the crystal lattice of Pr2O3. This result shows that the praseodymium oxide is predominantly present in single crystal form and is confirmed moreover by electron diffraction and high-resolution transmission electron microscope investigations (not shown here).
FIG. 2 shows the result of a capacitance-voltage (CV) measurement on a second, 13.4 nm thick Pr2O3 layer. Shown here is the dependency of the capacitance on the maximum amplitude of a high-frequency (100 kHz) voltage pulse Vg between an electrode which is described in greater detail hereinafter and the substrate, wherein the maximum amplitude of the high-frequency voltage pulse was increased and reduced respectively by 0.1 volt per second for recording the two illustrated curves. The present layer was deposited on p-doped (001)-silicon with a specific resistance of 10 ohms*centimeter under otherwise identical conditions to the layer shown in FIG. 1 and then provided with a gold electrode. The gold electrode was applied by the deposition of vaporised gold through a shadow mask. The measurement was effected after thermal curing. In the graph shown in FIG. 2 a solid line shows the CV curve with a first measuring run during which the maximum amplitude of the voltage pulse was reduced from 3 volts to −1 volt. A broken line in the graph shows the CV curve in the case of an immediately following second measuring run during which the maximum amplitude of the voltage pulse was increased from −1 volt to 3 volts. The capacitance of the layer is approximately 3000 picofarads with a voltage of −1 volt and it drastically falls from a voltage value of about −0.5 volt to values of around 200 picofarads at +0.5 volt. With a further increase in voltage the value of the capacitance falls slightly to a value of below 100 picofarads at 3 volts. The measurements are very substantially independent of the direction of the measuring run and show that no significant hysteresis effects occur.
FIG. 3 shows two X-ray spectra of the same kind as FIG. 1. They were measured on a third, 14.9 nm thick Pr2O3 layer on silicon, more specifically on the one hand (lower spectrum) in the untreated condition (‘as grown’) and on the other hand (upper spectrum) subsequently to a thermal treatment in a nitrogen atmosphere at a substrate temperature of 1000° C. over a period of time of 15 seconds. The X-ray spectrum of the treated layer is displaced upwardly in the direction of the ordinate solely to make the illustration clearer. It is shown in a comparison of the two spectra that the thermal treatment had no measurable influence on the crystalline structure of the treated sample. For, the two spectra are substantially identical. A worsening of the purity of the crystal structure would have been apparent on the basis of a widening of the peak to be associated with the Pr2O3, at about 2 theta=45°.