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AssigneeKabushiki Kaisha Toshiba
InventorsTomohisa Mizuno, Naoharu Sugiyama, Shinichi Takagi
Estimating the term…
A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes forming, on the first SiGe layer, a second SiGe layer which has a higher content of Ge than the first SiGe layer, forming a strained Si layer on the second SiGe layer, and forming a field effect transistor in which the strained Si layer is used a channel region. Further, a field effect transistor may be formed on a semiconductor substrate having an indefectible, high-quality, buried oxide layer and a largely strained Si layer, and hence a high-speed, low-power-consumption semiconductor device can be realized.
A method of manufacturing a semiconductor device, comprising:
A semiconductor device, comprising:
Dependencies are inferred from the claim text.
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Preparing SOI wafers: using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
Group IV materials, e.g. germanium or silicon carbide: having a multilayer structure or superlattice structure
Insulated-gate field-effect transistors [IGFET]: having composition variations in the channel regions
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being provided in or under the channel regions
Term end not estimated
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-075171, filed on Mar. 17, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing a semiconductor device.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
FIG. 1 is a cross-sectional view of a background semiconductor substrate;
FIG. 2 is a cross-sectional view illustrating the manufacturing process of a semiconductor device in accordance with the present invention;
Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, the present invention will be described.
In more detail, FIGS. 2-4 are cross-sectional views illustrating the manufacturing process of a semiconductor device, and FIG. 5 is a cross-sectional view illustrating the semiconductor device in accordance with the present invention.
First, a method of manufacturing a semiconductor substrate will be described. As shown in FIG. 2, a graded SiGe layer (third SiGe layer) 12 of 0.8 μm in thickness is epitaxially gown on a silicon wafer 11. Further, the content of Ge in the third SiGe layer 12 gradually increases from 0 atomic % to 10 atomic %.