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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKiyoshi Hayase
Estimating the term…
A comparator generates an event A when a value of a PC of a CPU matches a target address set in a target address register. If a trace is performed in a real-time trace mode in the initial state, an RS-FF is set by the generation of the event A and the trace will be performed in a full trace mode. Therefore, by setting a starting address of a subroutine for debugging in the target address register, the trace mode will be changed to the full trace mode when the CPU executes the subroutine, and thereby loss of trace information which will be important in debugging software can be prevented.
A trace device to generate trace information by switching between a full trace mode to generate trace information while stalling a processor, and a real-time trace mode to generate trace information while not stalling said processor, comprising:
A trace device to generate trace information of a processor by switching a trace mode to one of a branch trace mode, a data trace mode and a mixed trace mode, comprising:
A trace device to generate and output trace information of a processor, comprising:
Dependencies are inferred from the claim text.
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Debugging of software: by tracing the execution of the program
Computing and data processing
Term end not estimated
1. Field of the Invention
The present invention relates to a technique of generating trace information of a CPU (Central Processing Unit) used for debugging hardware having the CPU and for debugging software and, more specifically, to a trace device preventing loss of trace information which will be important in debugging.
2. Description of the Background Art
FIGS. 1-10 are block diagrams showing schematic structures of semiconductor devices respectively having trace devices in first to tenth embodiments of the present invention.
(First Embodiment)
FIG. 1 is a block diagram showing a schematic structure of a semiconductor device having a trace device in a first embodiment of the present invention. The semiconductor device includes a CPU 1, an event unit 2a, and a trace unit 3a. Hereinafter, event unit 2a and trace unit 3a are referred to as a trace device as a whole.
Event unit 2a includes target address registers 21a and 21b wherein target addresses are set, a comparator 22a to compare a value of a PC 11 of CPU 1 with the target address held in target address register 21a, and a comparator 22b to compare the value of PC 11 of CPU 1 with the target address held in target address register 21b. Target address registers 21a and 21b are accessible by CPU 1.