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US 2003/0192024 A1Published application
Configurable scan path structure
AssigneeTexas Instruments Incorporated
InventorAlessandro Paglieri
Life of this patent
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Abstract
A test structure is for a circuit (20) includes a scan configuration module (26), including routing circuitry (28) and control (30). The routing circuitry (28), under control of control circuitry (30) can be configured to route scan test signals to various scan core modules (36) over a selected number of input scan ports SI(N−1:0) and output scan ports SO(N−1:0). Thus, the number of scan ports used can be varied depending upon the tester being used.
Claims20
An integrated circuit comprising:
- logic circuitry having a plurality of defined logic cores;
- a plurality of input scan ports;
- a plurality of output scan ports;
- and
- routing circuitry for selectively routing test signals on said input scan ports through specified logic cores, such that the number of input scan ports used to pass test signals can programmably configured to optimize testing using various testers.
2 more elements
A method of testing in an integrated circuit, comprising the steps of:
- selectively enabling one or more of a plurality of input scan ports for receiving respective test signals;
- routing test signals on the selected input scan ports through specified logic cores, such that the number of input scan ports used to pass test signals can be programmably configured to optimize testing using various testers.
Dependencies are inferred from the claim text.