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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsAkihiro Goto, Takao Takahashi, Yoshio Matsuda, Takashi Arita, Koji Bando, Akinobu Kawazu
Estimating the term…
A design support apparatus, when designing multichip packages, verifies connections between a semiconductor chip and leads of a lead frame. Distances between two wires or distances between the wires and the other components are calculated using three-dimensional drawing data (CAD data) and semiconductor package data. Components of the semiconductor packages such as wires, lead frames, or die pads are drawn in the three-dimensional drawing data. The semiconductor package data describes specifications of the semiconductor packages such as outer sizes of the packages. Distance values are compared with design rule data. The design rule data defines constraints on the positional relationship between each wire and each component. The design support apparatus determines whether the acquired positional relationship is proper on the basis of design rule data.
A support apparatus for designing wires of a semiconductor device, the wire connecting a semiconductor chip to a lead frame in the semiconductor device, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Backward citations are indexed for grants only.
Circuit design: circuit design at the physical level
Interconnections or connectors in packages: bond wires
Shapes of wire connectors: the bond wires having kinks
On different surfaces: die-attach connectors and bond wires
Term end not estimated
1. Field of the Invention
The present invention relates to a support apparatus for designing semiconductor packages, in particular, for designing wires that connect semiconductor chips to a lead frame.
2. Background Art
The present invention will be more apparent from the following detailed description, when taken in conjunction with the accompanying drawings, in which;
FIG. 1 shows a system including a support apparatus according to one embodiment of the present invention;
FIGS. 2A, 2B, 2C and 2D, show an internal structure of a semiconductor package.
A preferred embodiment of the present invention will be described hereinafter with reference to the drawings.
FIGS. 2A, 2B, 2C and 2D, show an internal structure of a semiconductor package that comprises a lead frame. FIG. 2A is a top view, FIG. 2B is a perspective view, FIG. 2C is an enlarged side view, and FIG. 2D is a partially enlarged view of the perspective view of FIG. 2B. As shown in FIGS. 2A and 2B, the internal structure of the semiconductor package is configured such that semiconductor chips 23, 22 are mounted on a die pad 25 and each of the semiconductor chips is connected to leads 20 of a lead frame by wires 21. As shown in FIG. 2C, a semiconductor chip 24 is also mounted on the other side (underside) of the die pad 25, and, as shown in FIGS. 2C and 2D, the semiconductor chip 24 is also connected to the leads 20 of the lead frame by wires 21.
FIGS. 3, 4A, 4B, 5A, 5B, and 6 are simplified side views of semiconductor packages. FIG. 3 shows a one-chip type semiconductor package in which only one chip is mounted. Here, a chip 37 is mounted on a die pad (D/P) 35 and the chip 37 is connected to leads 36 by wires 34.