An apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs is provided. With the apparatus and method, latches are “colored,” i.e. classified into different types, based on information obtained from a clock tree of the circuit design. Clock tree primitives contain sufficient information to taxonomize the clocks into their respective phases and identify which latches are gated latches. In coloring the latches, gated latches are replaced in the circuit design with a free running clock, a multiplexor, and a sequence of L1 to Ln latches to provide a feedback path via the data path. This allows the gated latch to be phase abstracted without losing the “gated” functionality of the gated latch in the resulting trace. Once the latches are colored in this way, phase abstraction is performed on the colored circuit design. The phase abstracted netlist is then subjected to verification and a trace is produced. The coloring information of the original circuit, plus information as to the exact nature of the phase abstraction performed, is then used to transform the phase abstracted trace to one which resembles a trace of the circuit without phase abstraction.
Drawings
Claims29
A method of verifying a circuit design having at least one gated-clock latch, comprising:
receiving a clock tree for the circuit design;
identifying the at least one gated-clock latch based on information obtained from the clock tree;
replacing the at least one gated-clock latch with an explicit representation of a functionality of the gated-clock latch to thereby generate a modified circuit design;
performing phase abstraction on the modified circuit design;
and
verifying the circuit design based on the phase abstraction of the modified circuit design.
3 more elements
A computer program product in a computer readable medium for verifying a circuit design having at least one gated-clock latch, comprising:
first instructions for receiving a clock tree for the circuit design;
second instructions for identifying the at least one gated-clock latch based on information obtained from the clock tree;
third instructions for replacing the at least one gated-clock latch with an explicit representation of a functionality of the gated-clock latch to thereby generate a modified circuit design;
fourth instructions for performing phase abstraction on the modified circuit design;
and
fifth instructions for verifying the circuit design based on the phase abstraction of the modified circuit design.
3 more elements
An apparatus for verifying a circuit design having at least one gated-clock latch, comprising:
means for receiving a clock tree for the circuit design;
means for identifying the at least one gated-clock latch based on information obtained from the clock tree;
means for replacing the at least one gated-clock latch with an explicit representation of a functionality of the gated-clock latch to thereby generate a modified circuit design;
means for performing phase abstraction on the modified circuit design;
and
means for verifying the circuit design based on the phase abstraction of the modified circuit design.
#The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
#FIG. 1 is an exemplary block diagram of a computing apparatus according to the present invention;
#FIG. 2 is an exemplary diagram illustrating a process of verification of a circuit design;
Detailed description7,338 words
#With reference now to the figures, and in particular FIG. 1, a block diagram illustrating a data processing system is depicted in which the present invention may be implemented. Data processing system 100 is an example of a client computer. Data processing system 100 employs a peripheral component interconnect (PCI) local bus architecture. Although the depicted example employs a PCI bus, other bus architectures such as Accelerated Graphics Port (AGP) and Industry Standard Architecture (ISA) may be used. Processor 102 and main memory 104 are connected to PCI local bus 106 through PCI bridge 108. PCI bridge 108 also may include an integrated memory controller and cache memory for processor 102. Additional connections to PCI local bus 106 may be made through direct component interconnection or through add-in boards. In the depicted example, local area network (LAN) adapter 110, SCSI host bus adapter 112, and expansion bus interface 114 are connected to PCI local bus 106 by direct component connection. In contrast, audio adapter 116, graphics adapter 118, and audio/video adapter 119 are connected to PCI local bus 106 by add-in boards inserted into expansion slots. Expansion bus interface 114 provides a connection for a keyboard and mouse adapter 120, modem 122, and additional memory 124. Small computer system interface (SCSI) host bus adapter 112 provides a connection for hard disk drive 126, tape drive 128, and CD-ROM drive 130. Typical PCI local bus implementations will support three or four PCI expansion slots or add-in connectors.
#An operating system runs on processor 102 and is used to coordinate and provide control of various components within data processing system 100 in FIG. 1. The operating system may be a commercially available operating system, such as Windows 2000, which is available from Microsoft Corporation. An object oriented programming system such as Java may run in conjunction with the operating system and provide calls to the operating system from Java programs or applications executing on data processing system 100. “Java” is a trademark of Sun Microsystems, Inc. Instructions for the operating system, the object-oriented operating system, and applications or programs are located on storage devices, such as hard disk drive 126, and may be loaded into main memory 104 for execution by processor 102.
#Those of ordinary skill in the art will appreciate that the hardware in FIG. 1 may vary depending on the implementation. Other internal hardware or peripheral devices, such as flash ROM (or equivalent nonvolatile memory) or optical disk drives and the like, may be used in addition to or in place of the hardware depicted in FIG. 1. Also, the processes of the present invention may be applied to a multiprocessor data processing system.